ISP1583BS STEricsson, ISP1583BS Datasheet - Page 69

• Manufacturer Part Number: ISP1583BS
• Manufacturer: STEricsson

Specifications of ISP1583BS

• Lead Free Status / RoHS Status: Compliant

Table 102. ISP1583 register access timing parameters: separate address and data buses
V
ISP1583_10
Product data sheet
Symbol
Reading
t
t
t
t
t
t
RLRH
AVRL
RHAX
RLDV
RHDZ
RHSH
Fig 19. Receiver differential data jitter
CC(I/O)
= 1.65 V to 3.6 V; V
differential
data lines
T
+3.3 V
PERIOD
Parameter
RW_N/RD_N LOW pulse width
address set-up time before RW_N/RD_N LOW
address hold time after RW_N/RD_N HIGH
RW_N/RD_N LOW to data valid delay
RW_N/RD_N HIGH to data outputs 3-state delay
RW_N/RD_N HIGH to CS_N HIGH delay
0 V
13.1.1.1 8051 mode
13.1.1 Generic processor mode
13.1 Register access timing
is the bit duration corresponding to the USB data rate.
T
PERIOD
Remark: In the following subsections, RW_N/RD_N, DS_N/WR_N, READY/IORDY and
ALE/A0 refer to the ISP1583 pin.
BUS_CONF/DA0 = HIGH: generic processor mode
MODE0/DA1 = HIGH: 8051 mode; see
Fig 20. Receiver SE0 width tolerance
CC(3V3)
= 3.3 V; V
t
JR
N × T
consecutive
transitions
PERIOD
GND
= 0 V; T
+ t
Rev. 10 — 23 June 2009
JR1
differential
data lines
N × T
+3.3 V
amb
transitions
0 V
PERIOD
paired
=
−
40
+ t
Conditions
JR2
°
C to +85
Table 3
t
JR1
°
C; unless otherwise specified.
Hi-Speed USB peripheral controller
Min
> t
0
0
-
0
0
t
FST
RLDV
V
IH(min)
mgr872
Typ
-
-
-
-
-
-
© ST-ERICSSON 2009. All rights reserved.
t
JR2
ISP1583
Max
-
-
-
26
15
-
mgr871
69 of 97
Unit
ns
ns
ns
ns
ns
ns