ISP1583BS STEricsson, ISP1583BS Datasheet - Page 44

• Manufacturer Part Number: ISP1583BS
• Manufacturer: STEricsson

Specifications of ISP1583BS

• Lead Free Status / RoHS Status: Compliant

Table 47.
ISP1583_10
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Endpoint Type register: bit allocation
9.3.7 Endpoint Type register (address: 08h)
15
7
-
-
-
-
-
-
Table 46.
The ISP1583 supports all the transfers given in
Rev.
Each programmable FIFO can be independently configured using its Endpoint
MaxPacketSize register (R/W: 04h), but the total physical size of all enabled endpoints (IN
plus OUT), including set-up token buffer, control IN and control OUT, must not exceed
8192 bytes.
This register sets the endpoint type of the indexed endpoint: isochronous, bulk or
interrupt. It also serves to enable the endpoint and configure it for double buffering.
Automatic generation of an empty packet for a zero-length TX buffer can be disabled
using bit NOEMPKT. The register contains 2 bytes, and the bit allocation is shown in
Table
Bit
15 to 13
12 to 11
10 to 0
reserved
2.0”.
47.
14
6
-
-
-
-
-
-
Endpoint MaxPacketSize register: bit description
FFOSZ[10:0]
Symbol
-
NTRANS[1:0]
13
5
-
-
-
-
-
-
Rev. 10 — 23 June 2009
Description
reserved
Number of Transactions (HS mode only).
00 — 1 packet per microframe
01 — 2 packets per microframe
10 — 3 packets per microframe
11 — reserved
These bits are applicable only for isochronous or interrupt
transactions.
FIFO Size: Sets the FIFO size, in bytes, for the indexed endpoint.
Applies to both high-speed and full-speed operations.
NOEMPKT
R/W
12
4
0
0
-
-
-
reserved
ENABLE
R/W
11
3
0
0
-
-
-
Ref. 1 “Universal Serial Bus Specification
Hi-Speed USB peripheral controller
DBLBUF
R/W
10
2
0
0
-
-
-
© ST-ERICSSON 2009. All rights reserved.
R/W
9
1
0
0
-
-
-
ENDPTYP[1:0]
ISP1583
R/W
8
0
0
0
-
-
-
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