ISP1583BS STEricsson, ISP1583BS Datasheet - Page 57

• Manufacturer Part Number: ISP1583BS
• Manufacturer: STEricsson

Specifications of ISP1583BS

• Lead Free Status / RoHS Status: Compliant

Table 75.
ISP1583_10
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
DMA Interrupt Enable register: bit allocation
9.4.7 DMA Interrupt Enable register (address: 54h)
9.4.8 DMA Endpoint register (address: 58h)
TEST4
15
R
0
0
7
-
-
-
Table 73.
Table 74.
This 2-byte register controls the interrupt generation of the source bits in the DMA
Interrupt Reason register (see
description is given in
Logic 1 enables the interrupt generation. After a bus reset, interrupt generation is
disabled, with values turning to logic 0.
This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA
transfers. The bit allocation is given in
Bit
2
1
0
INT_EOT
1
1
0
reserved
14
6
-
-
-
-
-
-
Symbol
TF_RD_DONE
CMD_INTRQ_OK
-
reserved
DMA Interrupt Reason register: bit description
Internal EOT-functional relation with DMA_XFER_OK bit
DMA_XFER_OK
0
1
1
13
5
-
-
-
-
-
-
Table
Rev. 10 — 23 June 2009
IE_GDMA_
READ_1F0
73.
Description
Task File Read Done: Logic 1 indicates that the Read Task Files
command has been completed.
Command Interrupt OK: Logic 1 indicates that all bytes from the
FIFO have been transferred (DMA Transfer Count zero) and an
interrupt on pin INTRQ was detected.
reserved
Description
During the DMA transfer, there is a premature termination with
short packet.
DMA transfer is completed with short packet and the DMA
transfer counter has reached 0.
DMA transfer is completed without any short packet and the DMA
transfer counter has reached 0.
STOP
Table
R/W
R/W
IE_
12
0
0
4
0
0
72). The bit allocation is given in
Table
IE_EXT_
IE_BSY_
DONE
EOT
R/W
R/W
11
76.
0
0
3
0
0
Hi-Speed USB peripheral controller
RD_DONE
IE_INT_
IE_TF_
EOT
…continued
R/W
R/W
10
0
0
2
0
0
IE_INTRQ_
INTRQ_OK
PENDING
IE_CMD_
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
Table
9
0
0
1
0
0
ISP1583
75. The bit
XFER_OK
IE_DMA_
reserved
R/W
8
0
0
0
-
-
-
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