ISP1160BD/01,157 NXP Semiconductors, ISP1160BD/01,157 Datasheet - Page 15

• Manufacturer Part Number: ISP1160BD/01,157
• Manufacturer: NXP Semiconductors

Specifications of ISP1160BD/01,157

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

ISP1160-01_7
Product data sheet
Fig 13. HC interrupt logic.
HcInterruptEnable
HcInterruptStatus
register
register
RHSC
RHSC
FNO
FNO
MIE
RD
SO
RD
SO
UE
SF
UE
SF
There are two groups of interrupts represented by group 1 and group 2 in
pair of registers control each group.
Group 2 contains six possible interrupt events (recorded in the HcInterruptStatus register).
On occurrence of any of these events, the corresponding bit would be set to logic 1; and if
the corresponding bit in the HcInterruptEnable register is also logic 1, the 6-input OR gate
would output a logic 1. This output is AND-ed with the value of MIE (bit 31 of
HcInterruptEnable). Logic 1 at the AND gate will cause the OPR bit in the HcμPInterrupt
register to be set to logic 1.
Group 1 contains six possible interrupt events, one of which is the output of group 2
interrupt sources. The HcμPInterrupt and HcμPInterruptEnable registers work in the same
way as the HcInterruptStatus and HcInterruptEnable registers in the interrupt group 2. The
output from the 6-input OR gate is connected to a latch, which is controlled by
InterruptPinEnable (bit 0 of the HcHardwareConfiguration register).
In the event in which the software wishes to temporarily disable the interrupt output of the
ISP1160/01 Host Controller, the following procedure should be followed:
1. Make sure that the InterruptPinEnable bit in the HcHardwareConfiguration register is
2. Clear all bits in the HcμPInterrupt register.
3. Set the InterruptPinEnable bit to logic 0.
set to logic 1.
group 2
OR
Rev. 07 — 29 September 2009
INT
HcµPInterrupt
register
LATCH
OR
Embedded USB host controller
LE
HcµPInterruptEnable
HcHardwareConfiguration
register
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
InterruptPinEnable
register
Figure
004aaa102
13. A
15 of 87