ISP1160BD/01,157 NXP Semiconductors, ISP1160BD/01,157 Datasheet - Page 11

• Manufacturer Part Number: ISP1160BD/01,157
• Manufacturer: NXP Semiconductors

Specifications of ISP1160BD/01,157

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

ISP1160-01_7
Product data sheet
8.4 FIFO buffer RAM access by PIO mode
Most of the ISP1160/01’s internal control registers are 16-bit wide. Some of the internal
control registers, however, are 32-bit wide.
internal control register is accessed. The complete cycle of accessing a 32-bit register
consists of a command phase followed by two data phases. In the two data phases, the
microprocessor first reads or writes the lower 16-bit data, followed by the upper 16-bit
data.
To further describe the complete access cycles of the internal control registers, the status
of some pins of the microprocessor bus interface are shown in
Since the ISP1160/01’s internal memory is structured as a FIFO buffer RAM, the FIFO
buffer RAM is mapped to dedicated register fields. Therefore, accessing the internal FIFO
buffer RAM is similar to accessing the internal control registers in multiple data phases.
Fig 6.
Fig 7.
Fig 8.
data bus
Signals
CS_N
A0
RD_N,
WR_N
16-bit register access cycle.
32-bit register access cycle.
Accessing HC control registers.
write command
Rev. 07 — 29 September 2009
Command code
Valid status
(16 bits)
RD_N = 1,
WR_N = 0
0
1
write command
(16 bits)
16-bit register access cycle
32-bit register access cycle
read/write data
(lower 16 bits)
RD_N = 0 (read) or
WR_N = 0 (write)
Figure 7
Register data
Valid status
(lower word)
0
0
read/write data
shows how the ISP1160/01’s 32-bit
(16 bits)
Embedded USB host controller
read/write data
(upper 16 bits)
MGT937
Figure
RD_N = 0 (read) or
WR_N = 0 (write)
t
Register data
(upper word)
ISP1160/01
Valid status
© ST-ERICSSON 2009. All rights reserved.
8.
0
0
MGT938
t
004aaa370
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