FDC37C665GT Standard Microsystems (SMSC), FDC37C665GT Datasheet - Page 92

• Manufacturer Part Number: FDC37C665GT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C665GT

• Lead Free Status / RoHS Status: Not Compliant

The
incorporate one IBM XT/AT compatible parallel
port. The FDC37C665GT and FDC37C666GT
support the optional PS/2 type bi-directional
parallel port (SPP), the Enhanced Parallel Port
(EPP) and the Extended Capabilities Port (ECP)
parallel
FDC37C665GT Configuration Registers and
FDC37C666GT
description for information on disabling, power
down, changing the base address of the parallel
port, and selecting the mode of operation.
DATA PORT
STATUS PORT
CONTROL PORT
EPP ADDR PORT
The bit map of these registers is:
Note 1: These registers are available in all modes.
Note 2: These registers are only available in EPP mode.
Note 3 : For EPP mode, IOCHRDY must be connected to the ISA bus.
DATA PORT
STATUS
PORT
CONTROL
PORT
EPP ADDR
PORT
EPP DATA
PORT 0
EPP DATA
PORT 1
EPP DATA
PORT 2
EPP DATA
PORT 3
FDC37C665GT
port
STROBE AUTOFD
TMOUT
modes.
PD0
PD0
PD0
PD0
PD0
PD0
D0
Hardware
BASE ADDRESS + 00H
BASE ADDRESS + 01H
BASE ADDRESS + 02H
BASE ADDRESS + 03H
and
PD1
PD1
PD1
PD1
PD1
PD1
D1
0
Refer
FDC37C666GT
Configuration
nINIT
PD2
PD2
PD2
PD2
PD2
PD2
D2
to
0
PARALLEL PORT
the
nERR
PD3
SLC
PD3
PD3
PD3
PD3
PD3
D3
92
The FDC37C665GT and FDC37C666GT also
incorporate
which prevents possible damage to the parallel
port due to printer power-up.
The functionality of the Parallel Port is achieved
through the use of eight addressable ports,
with their associated registers and control
gating. The control and data port are read/write
by the CPU, the status port is read/write in the
EPP mode. The address map of the Parallel
Port is shown below:
EPP DATA PORT 0
EPP DATA PORT 1
EPP DATA PORT 2
EPP DATA PORT 3
SLCT
IRQE
PD4
PD4
PD4
PD4
PD4
PD4
D4
PCD
PD5
PD5
PD5
PD5
PD5
PD5
PE
SMSC's
D5
nACK
PD6
PD6
PD6
PD6
PD6
PD6
BASE ADDRESS + 04H
BASE ADDRESS + 05H
BASE ADDRESS + 06H
BASE ADDRESS + 07H
D6
0
ChiProtect
nBUSY
PD7
AD7
PD7
PD7
PD7
PD7
D7
0
circuitry,
Note
2,3
2,3
2,3
2,3
2,3
1
1
1