FDC37C665GT Standard Microsystems (SMSC), FDC37C665GT Datasheet - Page 34

• Manufacturer Part Number: FDC37C665GT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C665GT

• Lead Free Status / RoHS Status: Not Compliant

MAIN STATUS REGISTER
Address 3F4 READ ONLY
The Main Status Register is a read-only register
and indicates the status of the disk controller.
The Main Status Register can be read at any
BIT 0 - 3 DRV x BUSY
These bits are set to 1s when a drive is in the
seek portion of a command, including implied
and overlapped seeks and recalibrates.
BIT 4 COMMAND BUSY
This bit is set to a 1 when a command is in
progress.
command byte has been accepted and goes
inactive at the end of the results phase. If there
is
commands), this bit is returned to a 0 after the
last command byte.
DRATESEL
no
1
1
0
0
1
result
RQM
This bit will go active after the
Table 13 - Data Rates
7
0
1
0
1
0
phase
500 Kbps
300 Kbps
250 Kbps
1 Mbps
DIO
MFM
6
DATA RATE
(Seek,
NON
DMA
5
250 Kbps
150 Kbps
125 Kbps
Illegal
Recalibrate
FM
BUSY
CMD
4
34
BUSY
DRV3
time.
controller is ready to receive data via the Data
Register. It should be read before each byte
transferring to or from the data register except in
DMA mode. NO delay is required when reading
the MSR after a data transfer.
BIT 5 NON-DMA
This
command and will be set to a 1 during the
execution phase of a command.
polled data transfers and helps differentiate
between the data transfer phase and the reading
of result bytes.
BIT 6 DIO
Indicates the direction of a data transfer once a
RQM is set.
indicates a write is required.
BIT 7 RQM
Indicates that the host can transfer data if set to
a 1. No access is permitted if set to a 0.
Table 14 - Default Precompensation Delays
3
DATA RATE
500 Kbps
300 Kbps
250 Kbps
mode
1 Mbps
The MSR indicates when the disk
DRV2
BUSY
2
is
A 1 indicates a read and a 0
selected
DRV1
BUSY
PRECOMPENSATION
1
in
DELAYS
41.67 ns
125 ns
125 ns
125 ns
DRV0
BUSY
the
0
This is for
SPECIFY