ISP1760ETGA STEricsson, ISP1760ETGA Datasheet - Page 54

• Manufacturer Part Number: ISP1760ETGA
• Manufacturer: STEricsson

Specifications of ISP1760ETGA

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Table 61.
[1]
CD00222702
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Interrupt Enable register (address 0314h) bit allocation
INT_IRQ_E CLKREADY
8.4.2 Interrupt Enable register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Table 60.
This register allows enabling or disabling of the IRQ generation because of various events
as described in
Bit
2
1
0
R/W
R/W
R/W
R/W
_E
30
22
14
0
0
0
6
0
Symbol
-
SOFITL
INT
-
Interrupt register (address 0310h) bit description
HCSUSP_E
Table
R/W
R/W
R/W
R/W
29
21
13
Description
reserved; write reset value; value is zero just after reset and changes to one
after a short while
SOT ITL Interrupt: The IRQ line will be asserted if the respective enable bit
in the HCInterruptEnable register is set.
0 — No SOF event has occurred.
1 — An SOF event has occurred.
reserved; write reset value; value is zero just after reset and changes to one
after a short while
0
0
0
5
0
61.
reserved
Rev. 08 — 13 April 2010
reserved
[1]
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
[1]
DMAEOT
[1]
[1]
INT_E
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
Embedded Hi-Speed USB host controller
reserved
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
…continued
[1]
ISO_IRQ_E
SOFITLINT
© ST-ERICSSON 2010. All rights reserved.
R/W
R/W
R/W
R/W
_E
25
17
0
0
9
0
1
0
ISP1760
reserved
ATL_IRQ
R/W
R/W
R/W
R/W
54 of 105
24
16
_E
0
0
8
0
0
0
[1]