ISP1760ETGA STEricsson, ISP1760ETGA Datasheet - Page 51

• Manufacturer Part Number: ISP1760ETGA
• Manufacturer: STEricsson

Specifications of ISP1760ETGA

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Table 57.
CD00222702
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Port 1 Control register (address 0374h) bit allocation
8.3.14 Port 1 Control register
PORT1_
PORT1_
INIT2
INIT1
R/W
R/W
R/W
R/W
31
23
15
0
1
0
7
0
Table 56.
[1]
The values read from the lower 16 bits and the upper 16 bits of this register are always the
same.
Bit
2
1
0
[1]
For a 32-bit operation, the default wake-up counter value is 10 μs. For a 16-bit operation, the wake-up
counter value is 50 ms. In the 16-bit operation, read and write back the same value on initialization.
R/W
R/W
R/W
R/W
Table 57
30
22
14
0
0
0
6
0
Symbol
OC2_PWR
OC1_PWR
HC_CLK_
EN
reserved
Power Down Control register (address 0354h) bit description
shows the bit allocation of the register.
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Description
OC2_N Powered: Controls the powering of the overcurrent detection
circuitry for port 2.
0 — Overcurrent detection is powered-on or enabled during suspend.
1 — Overcurrent detection is powered-off or disabled during suspend.
This may be useful when connecting a faulty device while the system is in
standby.
OC1_N Powered: Controls the powering of the overcurrent detection
circuitry for port 1.
0 — Overcurrent detection is powered-on or enabled during suspend.
1 — Overcurrent detection is powered-off or disabled during suspend.
This may be useful when connecting a faulty device while the system is in
standby.
Host Controller Clock Enabled: Controls internal clocks during suspend.
0 — Clocks are disabled during suspend. This is the default value. Only
the LazyClock of 100 kHz ± 40 % will be left running in suspend if this bit is
logic 0. If clocks are stopped during suspend, CLKREADY IRQ will be
generated when all clocks are running stable.
1 — All clocks are enabled even in suspend.
Rev. 08 — 13 April 2010
PORT1_POWER[1:0]
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
1
reserved
reserved
reserved
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
Embedded Hi-Speed USB host controller
R/W
R/W
R/W
R/W
26
18
10
0
1
0
2
1
reserved
© ST-ERICSSON 2010. All rights reserved.
R/W
R/W
R/W
R/W
25
17
0
1
9
0
1
1
…continued
ISP1760
R/W
R/W
R/W
R/W
51 of 105
24
16
0
0
8
0
0
0