LPC47M112-MW Standard Microsystems (SMSC), LPC47M112-MW Datasheet - Page 34

• Manufacturer Part Number: LPC47M112-MW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M112-MW

• Lead Free Status / RoHS Status: Compliant

Enhanced Super I/O Controller with LPC Interface
Datasheet
DIGITAL INPUT REGISTER (DIR)
Address 3F7 READ ONLY
This register is read-only in all modes.
PC-AT Mode
BIT 0 - 6 UNDEFINED
The data bus outputs D0 - 6 are read as ‘0’.
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value
programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
PS/2 Mode
SMSC DS – LPC47M112
RESET
RESET
COND.
COND.
FIFO THRESHOLD
FIFO THRESHOLD
FIFO THRESHOLD
EXAMPLES
EXAMPLES
EXAMPLES
CHG
DSK
CHG
N/A
DSK
N/A
7
15 bytes
15 bytes
15 bytes
7
2 bytes
8 bytes
2 bytes
8 bytes
2 bytes
8 bytes
1 byte
1 byte
1 byte
N/A
N/A
6
1
Table 11 - FIFO Service Delay
6
0
DATASHEET
N/A
N/A
5
1
5
0
1 x 4 μs - 1.5 μs = 2.5 μs
2 x 4 μs - 1.5 μs = 6.5 μs
8 x 4 μs - 1.5 μs = 30.5 μs
15 x 4 μs - 1.5 μs = 58.5 μs
1 x 8 μs - 1.5 μs = 6.5 μs
2 x 8 μs - 1.5 μs = 14.5 μs
8 x 8 μs - 1.5 μs = 62.5 μs
15 x 8 μs - 1.5 μs = 118.5 μs
1 x 16 μs - 1.5 μs = 14.5 μs
2 x 16 μs - 1.5 μs = 30.5 μs
8 x 16 μs - 1.5 μs = 126.5 μs
15 x 16 μs - 1.5 μs = 238.5 μs
MAXIMUM DELAY TO SERVICING AT
MAXIMUM DELAY TO SERVICING AT
MAXIMUM DELAY TO SERVICING AT
Page 34
N/A
N/A
4
1
500 Kbps DATA RATE
4
0
2 Mbps DATA RATE
1 Mbps DATA RATE
N/A
N/A
3
1
3
0
DRATE
SEL1
N/A
N/A
2
2
0
DRATE
SEL0
N/A
N/A
1
1
0
nDENS
nHIGH
N/A
0
1
0
0
Rev. 02-16-07