LPC47M112-MW Standard Microsystems (SMSC), LPC47M112-MW Datasheet
LPC47M112-MW
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LPC47M112-MW Summary of contents
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... Kbps Data Rates - Programmable Precompensation Modes Keyboard Controller - 8042 Software Compatible - 8 Bit Microcomputer LPC47M112-MW for 100 pin QFP lead-free RoHS compliant package SMSC DS – LPC47M112 FEATURES - 2k Bytes of Program ROM 256 Bytes of Data RAM - Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface ...
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... REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC DS – LPC47M112 Page 3 DATASHEET Rev. 02-16-07 ...
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... FDC Internal Registers....................................................................................................................................25 10 COMMAND SET/DESCRIPTIONS ...................................................................................................................41 11 INSTRUCTION SET ..........................................................................................................................................44 12 SERIAL PORT (UART) .....................................................................................................................................62 13 Serial Data........................................................................................................................................................66 14 INFRARED INTERFACE ..................................................................................................................................75 15 MPU-401 MIDI UART........................................................................................................................................76 15.1 Overview.......................................................................................................................................................76 15.2 Host Interface...............................................................................................................................................76 ADDRESS.........................................................................................................................................................................................77 16 Status Port .......................................................................................................................................................78 17 Bits[5:0] ............................................................................................................................................................79 SMSC DS – LPC47M112 Page 4 DATASHEET Rev. 02-16-07 ...
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... TIMING DIAGRAMS .......................................................................................................................................177 32 PACKAGE OUTLINE......................................................................................................................................201 33 APPENDIX - TEST MODE ..............................................................................................................................202 33.1 Board Test Mode........................................................................................................................................202 List of Figures FIGURE 1 - LPC47M112 BLOCK DIAGRAM...............................................................................................................14 FIGURE 2 - MPU-401 MIDI INTERFACE ....................................................................................................................76 FIGURE 3 - MPU-401 INTERRUPT.............................................................................................................................79 FIGURE 4 - MIDI DATA BYTE EXAMPLE ...................................................................................................................81 FIGURE 5 – KEYBOARD LATCH ..............................................................................................................................112 SMSC DS – LPC47M112 Page 4 DATASHEET ...
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... Table 18 - Sector Sizes ................................................................................................................................................51 Table 19 - Effects of MT and N Bits ..............................................................................................................................51 Table 20 - Skip Bit vs Read Data Command.................................................................................................................51 Table 21 - Skip Bit vs. Read Deleted Data Command ...................................................................................................52 Table 22 - Result Phase...............................................................................................................................................53 Table 23 - Verify Command Result Phase ....................................................................................................................54 Table 24 - Typical Values for Formatting.......................................................................................................................55 SMSC DS – LPC47M112 Page 5 DATASHEET Rev. 02-16-07 ...
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... Table 57 - Runtime Register Block Summary ............................................................................................................132 Table 58 - Runtime Register Description ...................................................................................................................134 Table 59 - Game Port.................................................................................................................................................155 Table 60 – LPC47M112 Configuration Registers Summary.......................................................................................158 Table 61 - Chip Level Registers .................................................................................................................................161 Table 62 – Logical Device Registers...........................................................................................................................164 Table 63 - I/O Base Address Configuration Register Description.................................................................................166 Table 64 - Interrupt Select Configuration Register Description ...
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... There are 480 I/O address location options, a Serialized IRQ interface, and three DMA channels. The LPC47M112 does not require any external filter components and is therefore easy to use and offers lower system costs and reduced board area. The LPC47M112 is software and register compatible with SMSC's proprietary 82077AA core. SMSC DS – ...
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... GP42/nIO_PME 17 VTR 18 CLOCKI 19 LAD0 20 LAD1 21 LAD2 22 LAD3 23 nLFRAME 24 nLDRQ 25 nPCI_RESET 26 nLPCPD 27 GP43/DDRC 28 PCI_CLK 29 SER_IRQ 30 SMSC DS – LPC47M112 LPC47M10x LPC47M112 100 PIN QFP Page 8 DATASHEET nACK 80 BUSY SLCT 77 VSS 76 PD7 75 PD6 74 PD5 73 PD4 72 PD3 71 PD2 70 PD1 69 PD0 68 nSLCTIN 67 nINIT ...
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... Ground 40 Analog Ground 44 Reference Voltage 18 Trickle Voltage FDD INTERFACE (14) 16 Read Disk Data 11 Write Gate 10 Write Disk Data 12 Head Select 8 Step Direction SMSC DS – LPC47M112 TOTAL SYMBOL BUFFER 4 LAD[3:0] PCI_IO 1 nLFRAME PCI_I DMA 1 nLDRQ PCI_O 1 nPCI_RESE PCI_I T 1 nLPCPD ...
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... Set Ready 2 94 General Purpose I/O/Data Carrier Detect 2 92 General Purpose I/O/Ring Indicator 2 PARALLEL PORT INTERFACE (17) 66 Initiate Output 67 Printer Select Input 68 Port Data 0 69 Port Data 1 SMSC DS – LPC47M112 TOTAL SYMBOL BUFFER TYPE 1 nSTEP O12 1 nDSKCHG IS 1 nDS0 O12 1 nMTR0 O12 ...
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... General Purpose I/O /Joystick 2 Y-Axis 41 General Purpose I/O / P17 42 General Purpose I/O / P16 /nDS1 43 General Purpose I/O / P12/nMTR1 45 General Purpose I/O / System Option 46 General Purpose I/O /MIDI_IN SMSC DS – LPC47M112 TOTAL SYMBOL BUFFER TYPE 1 PD2 IOP14 1 PD3 IOP14 1 PD4 IOP14 1 PD5 IOP14 ...
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... POR). If the nKBDRST and A20M functions are to be used, the system must ensure that these pins are high. See Section “Pins That Require External Pullup Resistor”. Note 10: The LED pins are powered by VTR so that the LEDs can be controlled when the part is under VTR power. SMSC DS – LPC47M112 TOTAL SYMBOL ...
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... Open Collector Output nDIR if used as Open Collector Output nSTEP if used as Open Collector Output nWDATA if used as Open Collector Output nWGATE if used as Open Collector Output nHDSEL if used as Open Collector Output nINDEX nTRK0 nWRTPRT nRDATA nDSKCHG SMSC DS – LPC47M112 Page 13 DATASHEET Rev. 02-16-07 ...
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... Enhanced Super I/O Controller with LPC Interface Datasheet 4 BLOCK DIAGRAM SER_IRQ SERIAL IRQ PCI_CLK LPC Bus LPC BUS Signals INTERFACE V Vcc Vss TR FIGURE 1 - LPC47M112 BLOCK DIAGRAM SMSC DS – LPC47M112 FAN_TACH1* FAN1* Game Port Signals* FAN2* FAN_TACH2* ... (1-Dual) nIO_SMI nIO_PME Fan Control Game Port SMI ...
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... IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. 3. Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook. 4. PCI Bus Power Management Interface Specification, Rev. 1.0, Draft, March 18, 1997. 5. Low Pin Count (LPC) Interface Specification, Revision 1.0, September 29, 1997, Intel Document. SMSC DS – LPC47M112 Page 15 DATASHEET Rev. 02-16-07 ...
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... VOLT OPERATION / 5 VOLT TOLERANCE The LPC47M112 is a 3.3 Volt part intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that is, the input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected. The LPC interface pins are 3.3 Volt only. These signals meet PCI DC specifications for 3.3V signaling. These pins ...
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... See the following section for more information. 7.5 Indication of 32kHz Clock There is a bit to indicate whether or not the 32kHz clock input is connected to the LPC47M112. This bit is located at bit 0 of the CLOCKI32 register at 0xF0 in Logical Device A. This register is powered by VTR and reset on a VTR POR ...
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... Enhanced Super I/O Controller with LPC Interface Datasheet 7.6 Trickle Power Functionality When the LPC47M112 is running under VTR only (VCC removed), PME wakeup events are active and (if enabled) able to assert the nIO_PME pin active low. The following lists the wakeup events: UART 1 Ring Indicator ...
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... VREF Pin The LPC47M112 has a reference voltage pin input on pin 44 of the part. This reference voltage can be connected to either a 5V supply or a 3.3V supply used for the game port. See the “GAME PORT LOGIC” section. 7.8 Maximum Current Values See the “ ...
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... Host Processor Interface (LPC) The host processor communicates with the LPC47M112 through a series of read/write registers via the LPC interface. The port addresses for these registers are shown in Table 1. Register access is accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide. ...
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... DMA read cycles involve the transfer of data from the host (main memory) to the LPC47M112. DMA write cycles involve the transfer of data from the LPC47M112 to the host (main memory). Data will be coming from or going to a FIFO and will have minimal Sync times. Data transfers to/from the LPC47M112 are bytes. ...
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... DMA Protocol DMA on the LPC bus is handled through the use of the nLDRQ lines from the LPC47M112 and special encodings on LAD[3:0] from the host. The DMA mechanism for the LPC bus is described in the Low Pin Count (LPC) Interface Specification, Revision 1.0. ...
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... Enhanced Super I/O Controller with LPC Interface Datasheet If the host was reading data from the LPC47M112, data will still be transferred in the next two nibbles. This data may be invalid, but it will be transferred by the LPC47M112. If the host was writing data to the LPC47M112, the data had already been transferred ...
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... I/O Transfers The LPC47M112 inserts three wait states for an I/O read and two wait states for an I/O write cycle. A SYNC of 0110 is used for all I/O transfers. The exception to this is for transfers where IOCHRDY has been deasserted (i.e., EPP or IrCC transfers) in which case the sync pattern of 0110 is used and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of 10us) ...
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... Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction. BIT 1 nWRITE PROTECT Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected. SMSC DS – LPC47M112 R/W REGISTER R ...
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... Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset. BIT 6 DMA REQUEST Active high status of the DMA request pending. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt. SMSC DS – LPC47M112 DRQ ...
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... Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset. BIT 6 RESERVED Always read as a logic "1". BIT 7 RESERVED Always read as a logic "1". SMSC DS – LPC47M112 ...
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... This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. SMSC DS – LPC47M112 6 5 ...
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... This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 6 MOTOR ENABLE 2 The MTR2 disk interface output is not supported in the LPC47M112. BIT 7 MOTOR ENABLE 3 The MTR3 disk interface output is not supported in the LPC47M112. ...
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... Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps. SMSC DS – LPC47M112 DRIVE SELECT OUTPUTS (ACTIVE LOW) ...
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... DRIVE RATE DRT1 DRT0 SEL1 SMSC DS – LPC47M112 PRECOMPENSATION DELAY (nsec) <2Mbps 0.00 41.67 83.34 125.00 166.67 208.33 250.00 Default Default: See Table 10 Table 8 - Data Rates DATA RATE DATA RATE SEL0 MFM 1Meg --- 0 0 500 250 0 1 300 150 ...
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... Drive Meg Tape Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins. DT1 DT0 Table 10 - Default Precompensation Delays SMSC DS – LPC47M112 Table 9 - DRVDEN Mapping DRVDEN1 (1) DRVDEN0 (1) DRATE0 DENSEL DRATE0 DRATE1 DRATE0 nDENSEL DRATE1 DRATE0 PRECOMPENSATION DELAYS DATA RATE 2 Mbps 20 ...
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... An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered. SMSC DS – LPC47M112 5 4 ...
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... PS/2 Mode 7 DSK CHG RESET N/A COND. SMSC DS – LPC47M112 Table 11 - FIFO Service Delay MAXIMUM DELAY TO SERVICING AT 2 Mbps DATA RATE μs - 1.5 μs = 2.5 μ μs - 1.5 μs = 6.5 μ μs - 1.5 μs = 30.5 μ μs - 1.5 μs = 58.5 μs ...
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... PC/AT and PS/2 Modes 7 RESET N/A COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 8 for the appropriate values. BIT RESERVED Should be set to a logical "0" SMSC DS – LPC47M112 DMAEN NOPREC DRATE ...
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... During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. BIT NO. SYMBOL 7 1,0 DS1,0 SMSC DS – LPC47M112 N/A N/A N/A N/A Table 12 - Status Register 0 NAME DESCRIPTION Interrupt Code 00 - Normal termination of command. The specified command was properly executed and completed without error. ...
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... SMSC DS – LPC47M112 Table 13 - Status Register 1 NAME DESCRIPTION End of The FDC tried to access a sector beyond the final sector Cylinder of the track (255D). Will be set not issued after Read or Write Data command. Unused. This bit is always "0". Data Error The FDC detected a CRC error in either the ID field or the data field of a sector ...
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... DMA transfers are enabled with the Specify command and are initiated by the FDC by activating a DMA request cycle. DMA read, write and verify cycles are supported. The FDC supports two DMA transfer modes: Single Transfer and Burst Transfer. Burst mode is enabled via Logical Device 0-CRF0-Bit[1] (LD0-CRF0[1]). SMSC DS – LPC47M112 Table 15 - Status Register 3 NAME DESCRIPTION Unused. This bit is always " ...
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... FIFO. The DMA controller must respond to the request by reading data from the FIFO. The FDC will deactivate the DMA request when the FIFO becomes empty by generating the proper sync for the data transfer. SMSC DS – LPC47M112 Page 39 DATASHEET ...
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... RQM and DIO must both equal "1" before the result bytes may be read. After all the result bytes have been read, the RQM and DIO bits switch to "1" and "0" respectively, and the CB bit is cleared, indicating that the FDC is ready to accept the next command. SMSC DS – LPC47M112 Page 40 DATASHEET ...
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... Head Address HLT Head Load Time HUT Head Unload Time LOCK MFM MFM/FM Mode Selector SMSC DS – LPC47M112 DESCRIPTION The currently selected address 255. The pattern to be written in each sector data field during formatting. Designates which drives are perpendicular Perpendicular Mode Command. ...
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... Sectors Per Track SK Skip Flag SRT Step Rate Interval SMSC DS – LPC47M112 DESCRIPTION When set, this flag selects the multi-track operating mode. In this mode, the FDC treats a complete cylinder under head 0 and single track. The FDC operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1 ...
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... Status 2 ST3 Status 3 WGATE Write Gate SMSC DS – LPC47M112 DESCRIPTION Registers within the FDC which store status information after a command has been executed. This status information is available to the host during the result phase after command execution. Alters timing allow for pre-erase loads in perpendicular drives ...
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... D7 Command W MT MFM Execution Result SMSC DS – LPC47M112 Table 17 - Instruction Set READ DATA DATA BUS HDS DS1 DS0 ──────── C ──────── ──────── H ──────── ...
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... Command W MT MFM Execution Result SMSC DS – LPC47M112 WRITE DATA DATA BUS HDS DS1 DS0 ──────── C ──────── ──────── H ──────── ...
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... R PHASE R/W D7 Command W MT MFM Execution Result SMSC DS – LPC47M112 READ A TRACK DATA BUS MFM HDS DS1 ──────── C ──────── ──────── H ──────── ...
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... Result SMSC DS – LPC47M112 VERIFY DATA BUS ──────── H ──────── ──────── R ──────── ──────── N ──────── ...
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... ─── SRT ─── W PHASE R/W D7 Command Result R PHASE R/W D7 Command Execution PHASE R/W D7 Command Execution W SMSC DS – LPC47M112 RECALIBRATE DATA BUS DS1 SENSE INTERRUPT STATUS DATA BUS ─────── ST0 ─────── ...
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... Command W 0 Execution Result LOCK PHASE R/W D7 Command Execution Result SMSC DS – LPC47M112 RELATIVE SEEK DATA BUS DIR HDS DS1 ─────── RCN ─────── DUMPREG DATA BUS ────── PCN-Drive 0 ─────── ...
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... For reads, it continues to read the entire 128-byte sector and checks for CRC errors. For writes, it completes the 128-byte sector by filling in zeros not set to 00 Hex, DTL should be set to FF Hex and has no impact on the number of bytes transferred. SMSC DS – LPC47M112 PERPENDICULAR MODE DATA BUS ...
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... Table 20 - Skip Bit vs Read Data Command DATA ADDRESS SK BIT MARK TYPE VALUE ENCOUNTERED 0 Normal Data 0 Deleted Data SMSC DS – LPC47M112 Table 18 - Sector Sizes N SECTOR SIZE 00 128 bytes 01 256 bytes 02 512 bytes 03 1024 bytes .. ... 07 16 Kbytes ...
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... This command terminates when the EOT specified number of sectors has not been read. If the FDC does not find an ID Address Mark on the diskette after the second occurrence of a pulse on the INDEX pin, then it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command. SMSC DS – LPC47M112 RESULTS SECTOR ...
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... SC value of 0 will verify 256 sectors). This command can also be terminated by setting the EC bit to "0" and the EOT value equal to the final sector to be checked set to "0", DTL/SC should be programmed to 0FFH. Refer to Table 22 and Table 23 for information concerning the values of MT and EC versus SC and EOT value. Definitions: SMSC DS – LPC47M112 Table 22 - Result Phase ID INFORMATION AT RESULT PHASE HOST ...
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... FDC encounters a pulse on the nINDEX pin again and it terminates the command. Table 24 contains typical values for gap fields which are dependent upon the size of the sector and the number of sectors on each track. Actual values can vary due to drive electronics. SMSC DS – LPC47M112 SC/EOT VALUE TERMINATION RESULT Success Termination ...
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... CONTROL COMMANDS Control commands differ from the other commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. SMSC DS – LPC47M112 FORMAT FIELDS SYSTEM 34 (DOUBLE DENSITY) FORMAT SYNC ...
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... An interrupt signal is generated by the FDC for one of the following reasons: 1) Upon entering the Result Phase of: a. Read Data command b. Read A Track command c. Read ID command d. Read Deleted Data command e. Write Data command f. Format A Track command SMSC DS – LPC47M112 Page 56 DATASHEET Rev. 02-16-07 ...
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... Non-DMA mode uses the RQM bit and the interrupt to signal data transfers. Configure The Configure command is issued to select the special features of the FDC. A Configure command need not be issued if the default values of the FDC meet the system requirements. SMSC DS – LPC47M112 Table 25 - Interrupt Identification SE IC ...
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... The command is coded the same as for Seek, except for the MSB of the first byte and the DIR bit. DIR Head Step Direction Control RCN Relative Cylinder Number that determines how many tracks to step the head in or out from the current track number. SMSC DS – LPC47M112 Table 26 - Drive Control Delays (ms) HUT 500K 300K 250K ...
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... For the Write Data case, the FDC activates Write Gate at the beginning of the sync field under the conventional mode. The controller then writes a new sync field, data address mark, data field, and CRC. With the pre-erase head of the SMSC DS – LPC47M112 Page 59 DATASHEET Rev ...
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... DOR and DSR registers will not change the previously set parameters to their default values. All "hardware" RESET from the nPCI_RESET pin will set the LOCK bit to logic "0" and return the EFIFO, FIFOTHR, and PRETRK to SMSC DS – LPC47M112 Table 27 - Effects of WGATE and GAP Bits ...
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... DUMPREG command has been modified to contain the additional data from these two commands. COMPATIBILITY The LPC47M112 was designed with software compatibility in mind fully backwards- compatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems ...
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... Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial ports are defined by the configuration registers (see Configuration section). The Serial Port registers are located at sequentially increasing addresses above these base addresses. The LPC47M112 contains two serial ports, each of which contain a register set as described below. ...
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... Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the LPC47M112. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below ...
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... These two bits are set when the FIFO CONTROL Register bit 0 equals 1. FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER BIT 3 BIT 2 BIT 1 BIT SMSC DS – LPC47M112 RCVR FIFO Bit 7 Bit 6 Trigger Level (BYTES Table 29 - Interrupt Control INTERRUPT SET AND RESET FUNCTIONS PRIORITY INTERRUPT INTERRUPT LEVEL ...
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... LINE CONTROL REGISTER (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE Start LSB Data 5-8 bits MSB Parity Stop SMSC DS – LPC47M112 INTERRUPT SET AND RESET FUNCTIONS PRIORITY INTERRUPT INTERRUPT LEVEL TYPE SOURCE Second Character No Characters Timeout Have Been Indication Removed From or Input to the RCVR ...
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... Divisor Latch Access bit (DLAB). It must be set high (logic "1") to access the Divisor Latches of the Baud Rate Generator during read or write operations. It must be set low (logic "0") to access the Receiver Buffer Register, the Transmitter Holding Register, or the Interrupt Enable Register. SMSC DS – LPC47M112 BIT 1 BIT 0 ...
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... Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. The PE is set to a logic "1" upon detection of a parity error and is reset to a logic SMSC DS – LPC47M112 Page 67 DATASHEET Rev ...
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... Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed from logic "0" to logic "1". Bit 3 Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state. Note: Whenever bit set to a logic "1", a MODEM Status Interrupt is generated. SMSC DS – LPC47M112 Page 68 DATASHEET Rev. 02-16-07 ...
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... C. The receiver line status interrupt (IIR=06H), has higher priority than the received data available (IIR=04H) interrupt. D. The data ready bit (LSR bit 0) is set as soon as a character is transferred from the shift register to the RCVR FIFO reset when the FIFO is empty. SMSC DS – LPC47M112 Upon loading either of the Divisor Latches bit Baud counter is Page 69 DATASHEET Rev ...
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... FIFOs are still fully capable of holding characters. DESIRED DIVISOR USED TO GENERATE 16X CLOCK BAUD RATE 50 2304 75 1536 110 1047 134.5 857 150 768 SMSC DS – LPC47M112 Table 30 - Baud Rates PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL 0.001 - - 0.004 - Page 70 DATASHEET HIGH 1 2 SPEED BIT ...
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... The percentage error for all baud rates, except where indicated otherwise, is 0.2%. Note 2 : The High Speed bit is located in the Device Configuration Space. Note SMSC DS – LPC47M112 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL - - - - 0.005 - - - - - - 0 ...
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... FIFO Control Register (Write Only) ADDR = 3 Line Control Register ADDR = 4 MODEM Control Register ADDR = 5 Line Status Register ADDR = 6 MODEM Status Register SMSC DS – LPC47M112 Table 31 - Reset Function RESET CONTROL All bits low RESET Bit 0 is high; Bits low RESET All bits low RESET ...
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... Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip. Note 7: The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register (runtime register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x21). SMSC DS – LPC47M112 REGISTER SYMBOL SCR ...
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... Rx FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it. These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256 kbaud). SMSC DS – LPC47M112 Page 74 DATASHEET Rev. 02-16-07 ...
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... CRF2 in Logical Device 5. This register allows the time-out to be programmed to any value between 0 and 10msec in 100usec increments. IR Transmit Pins The following description pertains to the IRTX and IRTX2 pins of the LPC47M112. Following a VTR POR, the IRTX and IRTX2 pins will be output and low. They will remain low until one of the following conditions are met: IRTX2/GP35 Pin ...
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... The Sound Blaster 16 MPU-401 UART mode MIDI interface requires two consecutive I/O addresses with possible base I/O addresses of 300h and 330h. The default is 330h. The LPC47M112 MPU-401 I/O base address is programmable on even-byte boundaries throughout the entire I/O address range (see Section “Activate and I/O Base address” ...
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... An interrupt is generated when either MIDI receive data or a command acknowledge is available to the host in the MIDI Data register. See Section “Bit 7 – MIDI Receive Buffer Empty” and “Interrupt” TYPE R/W R/W MIDI DATA/COMMAND-ACKNOWLEDGE REGISTER NAME SMSC DS – LPC47M112 ADDRESS TYPE R Table 34 - MIDI Data Port MPU-401 I/O BASE ADDRESS D5 ...
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... Bit 6 – MIDI Transmit Busy Bit 6 MIDI Transmit Busy indicates the send (write) state of the MIDI Data port and Command port (Table 37). There are no interrupts associated with MIDI transmit (write) data. STATUS PORT SMSC DS – LPC47M112 Table 35 - MPU-401 Status Port ...
Page 79
... MIDI Data register. Note 3 IRQ is the MPU-401 Host Interface IRQ shown in Figure 2. The UART Receive FIFO Threshold = 1. Note 4 MIDI RX CLOCK is the MIDI bit clock. The MIDI bit clock period is 32μs. Note SMSC DS – LPC47M112 Table 38 – MPU-401 Command Port ...
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... Data port. For example if the receive FIFO is not empty when an MPU-401 RESET command is received, the command acknowledge will appear first, before any unread FIFO data. In the examples above, the receive FIFO is cleared before the command acknowledge byte is placed in the MIDI Data port read buffer. SMSC DS – LPC47M112 Page 80 DATASHEET The MPU-401 Command Rev ...
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... MPU-401 Configuration Registers The LPC47M112 configuration registers are in Logical Device B (see Configuration section). The configuration registers contain the MPU-401 Activate, Base Address and Interrupt select. The defaults for the Base Address and Interrupt Select configuration registers match the MPU-401 factory defaults. ...
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... Datasheet 18 PARALLEL PORT The LPC47M112 incorporates an IBM XT/AT compatible parallel port. directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation ...
Page 83
... BIT 4 SLCT - PRINTER SELECTED STATUS The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means the printer is on line; a logic 0 means it is not selected. SMSC DS – LPC47M112 Table 39 - Parallel Port Connector STANDARD EPP ...
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... PD7 ports are read. An LPC I/O read cycle causes an EPP ADDRESS READ cycle to be performed and the data output to the host CPU, the deassertion of ADDRSTB latches the PData for the duration of the read cycle. This register is only available in EPP mode. SMSC DS – LPC47M112 Page 84 DATASHEET The address register is cleared at Rev ...
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... The write can complete once nWAIT is determined inactive. Write Sequence of operation 1. The host initiates an I/O write cycle to the selected EPP register WAIT is not asserted, the chip must wait until WAIT is asserted. SMSC DS – LPC47M112 Page 85 DATASHEET Rev. 02-16-07 ...
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... TAR to complete the write cycle. 7. Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle. 8. Chip may modify nWRITE and nPDATA in preparation for the next cycle. SMSC DS – LPC47M112 Page 86 DATASHEET Rev. 02-16-07 ...
Page 87
... The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. The chip inserts wait states into the I/O read cycle when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The read cycle can complete when nWAIT is inactive high. SMSC DS – LPC47M112 Page 87 DATASHEET ...
Page 88
... The following terms are used in this document: assert: When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state. forward: Host to Peripheral communication. reverse: Peripheral to Host communication SMSC DS – LPC47M112 Table 40 - EPP Pin Descriptions TYPE EPP DESCRIPTION O This signal is active low. It denotes a write operation. ...
Page 89
... The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte repeated. SMSC DS – LPC47M112 D5 D4 ...
Page 90
... I (nPeriphRequest) nInit O nSelectIn O SMSC DS – LPC47M112 Table 41 - ECP Pin Descriptions DESCRIPTION During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). Contains address or data or RLE data. Indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse ...
Page 91
... The operation of this register is only defined for the forward direction (direction is 0). Refer to the ECP Parallel Port Forward Timing Diagram, located in the Timing Diagrams section of this data sheet. SMSC DS – LPC47M112 Table 42 - ECP Register Definitions ECP MODES ...
Page 92
... Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. Transfers to the FIFO are byte aligned. This mode is only defined for the forward direction. SMSC DS – LPC47M112 Page 92 DATASHEET Rev. 02-16-07 ...
Page 93
... BITS [5:3] Parallel Port IRQ (read-only) Refer to Table 44B. BITS [2:0] Parallel Port DMA (read-only) Refer to Table 44C. ecr (Extended Control Register) ADDRESS OFFSET = 402H Mode = all This register controls the extended ECP parallel port functions. SMSC DS – LPC47M112 Page 93 DATASHEET Rev. 02-16-07 ...
Page 94
... Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted on the parallel port. All drivers have active pull-ups (push-pull). 111: Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401. All drivers have active pull-ups (push-pull). SMSC DS – LPC47M112 Table 44A - Extended Control Register MODE Page 94 DATASHEET ...
Page 95
... Termination from ECP Mode is similar to the termination from Nibble/Byte Modes. The host is permitted to terminate from ECP Mode only in specific well-defined states. The termination can only be executed while the bus is in the forward direction. To terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction. SMSC DS – LPC47M112 BITS 5:3 DMA ...
Page 96
... FIFO. b.(1) When serviceIntr is 0, dmaEn is 0, direction is 1 and there are readIntrThreshold or more bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are readIntrThreshold or more bytes in the FIFO. SMSC DS – LPC47M112 D7 D[6:0] 0 Run-Length Count ...
Page 97
... The ECP requests programmed I/O transfers from the host by activating the interrupt. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. Note: A threshold equivalent to a threshold of 15. These two cases are treated the same. SMSC DS – LPC47M112 Page 97 DATASHEET ...
Page 98
... FIFO this time the FIFO is empty, it can be completely filled in a single burst, otherwise a minimum of (16-<threshold>) bytes may be written to the FIFO in a single burst. This process is repeated until the last byte is transferred into the FIFO. SMSC DS – LPC47M112 Page 98 DATASHEET ...
Page 99
... The pins of the LPC47M112 can be divided into two major categories: system interface and floppy disk drive interface. The floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any voltage applied SMSC DS – ...
Page 100
... Pins used for local logic control or part programming are unaffected. Table 48 depicts the state of the floppy disk drive interface pins in the powerdown state. Table 48 - State of Floppy Disk Drive Interface Pins in Powerdown FDD PINS nRDATA nWRTPRT nTRK0 nINDEX nDSKCHG nMTR0 nDS0 SMSC DS – LPC47M112 AVAILABLE REGISTERS PC-AT PS/2 (MODEL 30) ---- SRA ---- SRB DOR (1) DOR (1) --- ...
Page 101
... The parallel port logic can change powerdown modes when the ECP mode is changed through the ecr register or when the parallel port mode is changed through the configuration registers. Serial IRQ The LPC47M112 supports the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. SMSC DS – LPC47M112 ...
Page 102
... Note 1: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn- around clock of the Stop Frame. Note 2: There may be none, one or more Idle states during the Stop Frame. Note 3: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode. SMSC DS – LPC47M112 IRQ0 FRAME IRQ1 FRAME R T ...
Page 103
... Stop Frames pulse width to determine the next SER_IRQ Cycle’s mode. SER_IRQ Data Frame Once a Start Frame has been initiated, the LPC47M112 will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase ...
Page 104
... SER_IRQ Cycle is performed. For SER_IRQ system suspend, insertion, or removal application, the Host controller should be programmed into Continuous (IDLE) mode first. This is to guarantee SER_IRQ bus is in IDLE state before the system configuration changes. SMSC DS – LPC47M112 Page 104 DATASHEET Rev. 02-16-07 ...
Page 105
... Enhanced Super I/O Controller with LPC Interface Datasheet 21 8042 KEYBOARD CONTROLLER DESCRIPTION The LPC47M112 is a Super I/O and Universal Keyboard Controller that is designed for intelligent keyboard management in desktop computer applications. The Universal Keyboard Controller uses an 8042 microcontroller CPU core. LPC47M112 enhancements to the 8042. For general information about the 8042, refer to the "Hardware Description of the 8042" ...
Page 106
... If "EN FLAGS" has been executed and P24 is set to a one: the OBF flag is gated onto KIRQ. The KIRQ signal can be connected to system interrupt to signify that the LPC47M112 CPU has written to the output data register via "OUT DBB,A". If P24 is set to a zero, KIRQ is forced low. On power-up, after a valid RST pulse has been delivered to the device, KIRQ is reset to 0. KIRQ will normally reflects the status of writes " ...
Page 107
... If "EN FLAGS" has been executed and P25 is set to a one:; IBF is inverted and gated onto MIRQ. The MIRQ signal can be connected to system interrupt to signify that the LPC47M112 CPU has read the DBB register. If "EN FLAGS” has not been executed, MIRQ is controlled by P25, Writing a zero to P25 forces MIRQ low, a high forces MIRQ high. (MIRQ is normally selected as IRQ12 for mouse support) ...
Page 108
... Keyboard Data or Command Write Buffer and clear the IBF flag. Refer to the KIRQ and Status register descriptions for more information. Host I/F Status Register The Status register is 8 bits wide. Table 51 shows the contents of the Status register. SMSC DS – LPC47M112 Page 108 DATASHEET Rev. 02-16-07 ...
Page 109
... In powerdown mode, the external clock signal is not loaded by the chip. DEFAULT RESET CONDITIONS The LPC47M112 has one source of hardware reset: an external reset via the nPCI_RESET pin. Refer to Table 46 for the effect of each type of reset on the internal registers. ...
Page 110
... Enhanced Super I/O Controller with LPC Interface Datasheet GATEA20 AND KEYBOARD RESET The LPC47M112 provides two options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and KRESET and Port 92 Fast GateA20 and KRESET. PORT 92 FAST GATEA20 AND KEYBOARD RESET Port 92 Register This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register (Logical Device 7, 0xF0) set to 1 ...
Page 111
... Register forces ALT_A20 high. ALT_A20 high drives nA20M to the CPU high, regardless of the state of A20GATE from the keyboard controller. Upon reset, this signal is driven low. 21.1 Latches On Keyboard and Mouse IRQs The implementation of the latches on the keyboard and mouse interrupts is shown below. SMSC DS – LPC47M112 14us 6us KRST KRST_GA20 ...
Page 112
... Bit[4]: MLATCH – Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ANDed with Latched MINT (default), 1=MINT is the latched 8042 MINT. Bit[3]: KLATCH – Keyboard Interrupt latch control bit. 0=KINT is the 8042 KINT ANDed with Latched KINT (default), 1=KINT is the latched 8042 KINT. SMSC DS – LPC47M112 KLATCH Bit VCC D ...
Page 113
... PME events. The LPC47M112 has “isolation” bits for the keyboard and mouse signals, which allow the keyboard and mouse data signals to go into the wakeup logic but block the clock and data signals from the 8042. These bits may be used anytime it is necessary to isolate the 8042 keyboard and mouse signals from the 8042 before entering a system sleep state ...
Page 114
... Datasheet 22 GENERAL PURPOSE I/O The LPC47M112 provides a set of flexible Input/Output control functions to the system designer through the 37 dedicated independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and many of them can be individually enabled to generate an SMI and a PME. ...
Page 115
... Fan Speed Control 1 61 GPIO Infrared Rx 62 Infrared Tx GPIO 63 GPIO Keyboard Reset 64 GPIO Gate A20 SMSC DS – LPC47M112 The GPIO ports with their alternate functions and ALT. ALT. DATA 1 FUNC. 2 FUNC. 3 REGISTER GP1 GP2 EETI EETI GP3 Page 115 DATASHEET DATA ...
Page 116
... GP43, the analog game port pins (J1X, J1Y, J2X, J2Y) and the either edge triggered interrupts. When the alternate function is selected for the analog joystick pins (GP14, GP15, GP16 and GP17), these pins become open drain, non-inverted outputs. The basic GPIO configuration options are summarized in Table 54. SMSC DS – LPC47M112 ALT. ALT. DATA 1 FUNC ...
Page 117
... GPIO data register is output to the GPIO pin. Reading from a GPIO port that is programmed as an output returns the last value written to the data register (Table 57). When the GPIO is programmed as an output, the pin is excluded from the PME and SMI logic. HOST SMSC DS – LPC47M112 Table 54 - GPIO Configuration Summary POLARITY BIT ...
Page 118
... WRITE NO EFFECT The LPC47M112 provides 31 GPIOs that can directly generate a PME. See the table in the next section. The polarity bit in the GPIO control registers select the edge on these GPIO pins that will set the associated status bit in the PME_STS 2 register. The default is the low-to-high edge. If the corresponding enable bit in the PME_EN 2 register and the PME_EN bit in the PME_EN register is set, a PME will be generated ...
Page 119
... Led Functionality The LPC47M112 provides LED functionality on two GPIOs, GP60 and GP61. These pins can be configured to turn the LED on and off and blink independent of each other through the LED1 and LED2 runtime registers at offset 0x5D and 0x5E from the base address located in the primary base I/O address in Logical Device A. ...
Page 120
... VCC or VTR, since the buffers for these pins are powered by VTR. This means they will source their specified current from VTR even when VCC is present. The LED control registers are defined in the “Runtime Register” section. SMSC DS – LPC47M112 Page 120 DATASHEET ...
Page 121
... Datasheet 23 SYSTEM MANAGEMENT INTERRUPT (SMI) The LPC47M112 implements a “group” nIO_SMI output pin. The System Management Interrupt is a non-maskable interrupt with the highest priority level used for OS transparent power management. The nIO_SMI group interrupt output consists of the enabled interrupts from each of the functional blocks in the chip and many of the GPIOs and the Fan tachometer pins ...
Page 122
... See the “Keyboard and Mouse PME Generation” section for information about using the keyboard and mouse signals to generate a PME. In the LPC47M112 the nIO_PME pin can be programmed open drain, active low, driver. The LPC47M112 nIO_PME pin is fully isolated from other external devices that might pull the nIO_PME signal low; i.e., the nIO_PME signal is capable of being driven high externally by another active device or pullup even when the LPC47M112 VCC is grounded, providing VTR power is active ...
Page 123
... On Specific Key’ Option The LPC47M112 has logic to detect a single keyboard scan code for wakeup (PME generation). The scan code is programmed onto the Keyboard Scan Code Register, a runtime register at offset 0x5F from the base address located in the primary base I/O address in Logical Device A. This register is powered by VTR and reset on VTR POR. ...
Page 124
... Note: The generation of a PME for this event is controlled by the PME enable bit (located in the PME_EN1 register at bit 5) when the logic for feature is turned on. SMSC DS – LPC47M112 Page 124 DATASHEET Rev. 02-16-07 ...
Page 125
... Multiplier bits in the Fan Control register to determine the fan speed F 25.1.1.2 Duty Cycle Control for Fan x, Bits D6 – D1 The Duty Cycle Control (DCC) bits determine the fan duty cycle. The LPC47M112 has ≈1.56% duty cycle resolution. When DCC = “000000” (min. value high ...
Page 126
... Clock Select bit in the Fan x registers to determine the fan speed F 25.2 Fan Tachometer Inputs The LPC47M112 implements fan tachometer inputs for signals from fans equipped with tachometer outputs. The part can generate both a PME and an SMI when the fan speed drops below a predetermined value. See description below. ...
Page 127
... Term 1 in Equation 1 for the example above will be 160. Therefore, the preload value is chosen that when the count reaches 192, this will correspond to 70% of the normal RPM for the generation of a PME or SMI. A representation of the logic for the fan tachometer implementation is shown below. 32 kHz SMSC DS – LPC47M112 6 + Preload (Equation 1) Preload ...
Page 128
... Divide by 8 1100 Pins 51 and 52 are the fan tachometer inputs, FAN_TACH2 and FAN_TACH1, respectively. The configuration registers for the fan tachometer inputs are defined in the “Runtime Registers” section. SMSC DS – LPC47M112 TERM 1 FOR “DIVIDE BY 2” PRELOAD (DEFAULT) IN DECIMAL ...
Page 129
... Enhanced Super I/O Controller with LPC Interface Datasheet 26 SECURITY FEATURE The following register describes the functionality to support security in the LPC47M112. 26.1 GPIO Device Disable Register Control The GPIO pin GP43 is used for the Device Disable Register Control (DDRC) function. Setting bits[3:2] of the GP43 configuration register to ‘ ...
Page 130
... Datasheet 27 GAME PORT LOGIC The LPC47M112 implements logic to support a dual game port. This logic includes the following for each game port: two 555 timers, two game port RC constant inputs (x-axis and y-axis), two game port button inputs and game port interface logic. The implementation of the Game Port uses a simple A/D converter constructed from a 555 timer to digitize the analog value of a potentiometer for the x-axis and y-axis of the joystick ...
Page 131
... VREF Pin The LPC47M112 has a reference voltage pin input on pin 44 of the part. This reference voltage can be connected to either a 5V supply or a 3.3V supply used for the game port. The reference voltage is used in the game port logic so that the joystick trigger voltage is 2/3 VREF where VREF is either ...
Page 132
... Enhanced Super I/O Controller with LPC Interface Datasheet 28 RUNTIME REGISTERS The following registers are runtime registers in the LPC47M112. They are located at the address programmed in the Base I/O Address in Logical Device A at the offset shown. These registers are powered by VTR. Table 57 - Runtime Register Block Summary ...
Page 133
... R/W 46 R/W 47 R R/W 4C R/W Note 2 4D R/W 4E R/W Note 3 4F R R/W 57 R R/W 5C R/W SMSC DS – LPC47M112 VCC SOFT POR RESET VTR POR - - 0x01 - - - 0x01 - - - 0x01 - - - - - - - 0x01 - - - 0x01 - - - 0x01 - - - 0x01 - - - 0x01 - - - 0x01 - 0x00 0x01 - 0x00 0x01 ...
Page 134
... Table 58 - Runtime Register Description (hex) DESCRIPTION 00 Bit[0] PME_Status = 0 (default) (R/ Set when LPC47M112 would normally assert the nIO_PME signal, independent of the state of the PME_En bit. Bit[7:1] Reserved PME_Status is not affected by Vcc POR, SOFT RESET or HARD RESET. Writing a “1” to PME_Status will clear it and cause the LPC47M112 to stop asserting nIO_PME, in enabled. Writing a “ ...
Page 135
... Default = 0x00 on VTR POR PME_STS2 Default = 0x00 on VTR POR PME_STS3 Default = 0x00 on VTR POR SMSC DS – LPC47M112 (hex) DESCRIPTION 04 PME Wake Status Register 1 This register indicates the state of the individual PME wake (R/W) sources, independent of the individual source enables or the PME_En bit. ...
Page 136
... Reserved – reads return 0 (R) 0A PME Wake Enable Register 1 This register is used to enable individual LPC47M112 PME (R/W) wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active (“1”), if the source asserts a wake event so that the associated status bit is “ ...
Page 137
... The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or HARD RESET. 0C PME Wake Status Register 3 This register is used to enable individual LPC47M112 PME (R/W) wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active (“ ...
Page 138
... The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or HARD RESET. 0E PME Wake Enable Register 5 This register is used to enable individual LPC47M112 PME (R/W) wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active (“ ...
Page 139
... VTR POR (Note 6) SMI_STS5 Default = 0x00 on VTR POR N/A SMI_EN1 Default = 0x00 on VTR POR SMSC DS – LPC47M112 (hex) DESCRIPTION 11 SMI Status Register 2 This register is used to read the status of the SMI inputs. (R/W) Bit[0] MINT. Cleared at source. Bit[1] KINT. Cleared at source. Bit[2] IRINT. This bit is set by a transition on the IR pin (IRRX or IRRX2 as selected in CR L5-F1-B6 i ...
Page 140
... VTR POR SMI_EN4 Default = 0x00 on VTR POR SMI_EN5 Default = 0x00 on VTR POR N/A SMSC DS – LPC47M112 (hex) DESCRIPTION 17 SMI Enable Register 2 This register is used to enable the different interrupt sources onto the group nSMI output, and the group nSMI output onto (R/W) the nIO_SMI GPI/O pin, the serial IRQ stream or into the PME Logic ...
Page 141
... Default = 0x01 on VCC POR Floppy Data Rate Select Shadow UART1 FIFO Control Shadow SMSC DS – LPC47M112 (hex) DESCRIPTION 1C Miscellaneous Status Register Bits[5:0] can be cleared by writing their position (R/W) (writing a 0 has no effect). Bit[0] Either Edge Triggered Interrupt Input 0 Status. This bit is set when an edge occurs on the GP21 pin. ...
Page 142
... GP43 register bits[3:2] ≠ 01 READ-ONLY When GP43 register bits[3:2] =01 AND GP43 pin = 1 GP10 Default = 0x01 on VTR POR SMSC DS – LPC47M112 (hex) DESCRIPTION 21 UART FIFO Control Shadow 2 Bit[0] FIFO Enable (R) Bit[1] RCVR FIFO Reset Bit[2] XMIT FIFO Reset Bit[3] DMA Mode Select ...
Page 143
... GP13 Default = 0x01 on VTR POR GP14 Default = 0x01 on VTR POR GP15 Default = 0x01 on VTR POR SMSC DS – LPC47M112 (hex) DESCRIPTION 24 General Purpose I/0 bit 1.1 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[2] Alternate Function Select 1= J1B2 (Joystick 1, Button 2) ...
Page 144
... Default = 0x01 on VTR POR GP21 Default =0x01 on VTR POR GP22 Default =0x01 on VTR POR N/A SMSC DS – LPC47M112 (hex) DESCRIPTION 29 General Purpose I/0 bit 1.6 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[2] Alternate Function Select 1= J2X (Joystick 2, X-Axis RC Constant) ...
Page 145
... VTR POR GP27 Default = 0x01 on VTR POR GP30 Default = 0x01 on VTR POR GP31 Default = 0x01 on VTR POR SMSC DS – LPC47M112 (hex) DESCRIPTION 2F General Purpose I/0 bit 2.4 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[2] Reserved Bits[6:3] Reserved Bit[7] Output Type Select ...
Page 146
... VTR POR GP35 Default = 0x04 on VTR POR, VCC POR and Hard Reset (Note 3) GP36 Default = 0x01 on VTR POR SMSC DS – LPC47M112 (hex) DESCRIPTION 35 General Purpose I/0 bit 3.2 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[2] Alternate Function Select 1=FAN2 ...
Page 147
... VTR POR GP40 Default =0x01 on VTR POR GP41 Default =0x01 on VTR POR GP42 Default =0x01 on VTR POR SMSC DS – LPC47M112 (hex) DESCRIPTION 3A General Purpose I/0 bit 3.7 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[2] Alternate Function Select 1=A20M ...
Page 148
... GP50 Default = 0x01 on VTR POR GP51 Default = 0x01 on VTR POR GP52 Default = 0x01 on VTR POR SMSC DS – LPC47M112 (hex) DESCRIPTION 3E General Purpose I/0 bit 4.3 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[3:2] Alternate Function Select 11=Either Edge Triggered Interrupt Input 3 (Note 1), 10= Reserved 01=Device Disable Register Control ...
Page 149
... GP54 Default = 0x01 on VTR POR GP55 Default = 0x01 on VTR POR GP56 Default = 0x01 on VTR POR SMSC DS – LPC47M112 (hex) DESCRIPTION 42 General Purpose I/0 bit 5.3 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[3:2] Alternate Function Select 11= Reserved 10= Reserved ...
Page 150
... Default = 0x01 on VTR POR N/A N/A GP1 Default = 0x00 on VTR POR GP2 Default = 0x00 on VTR POR SMSC DS – LPC47M112 (hex) DESCRIPTION 46 General Purpose I/0 bit 5.7 Bit[0] In/Out : =1 Input, =0 Output (R/W) Bit[1] Polarity : =1 Invert Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Reserved ...
Page 151
... VTR POR GP6 Default = 0x00 on VTR POR N/A N/A N/A N/A N/A FAN1 Default = 0x00 on VTR POR SMSC DS – LPC47M112 (hex) DESCRIPTION 4D General Purpose I/0 Data Register 3 Bit[0] GP30 (R/W) Bit[1] GP31 Bit[2] GP32 Bit[3] GP33 Bit[4] GP34 Bit[5] GP35 ...
Page 152
... FAN2 Default = 0x00 on VTR POR Fan Control Default = 0x50 on VTR POR Fan1 Tachometer Register Default = 0x00 on VTR POR SMSC DS – LPC47M112 (hex) DESCRIPTION 57 FAN Register 2 Bit[0] Fan Control (R/W) 1=FAN2 pin is high 0=bits[6:1] control the duty cycle of the FAN2 pin. Bit[6:1] Duty Cycle Control for FAN2 ...
Page 153
... GP 62 simultaneously. If P17 is selected on GP20 and GP62, simultaneously, then P17 on GP62 will function and P17 on GP20 will not. Note 1: If the EETI function is selected for this GPIO then both a high-to-low and a low-to-high edge will set the PME, SMI and MSC status bits SMSC DS – LPC47M112 (hex) DESCRIPTION 5A Fan Tachometer Register 2 Bit[7:0] The 8-bit FAN2 tachometer count ...
Page 154
... VCC POR since these pins revert to their non-inverting GPIO output function when VCC is removed from the part. These GPIOs cannot be used for PME wakeup when the part is under VTR power (VCC=0). Note 7: These bits are R/W but have no effect on circuit operation. SMSC DS – LPC47M112 Page 154 DATASHEET Rev. 02-16-07 ...
Page 155
... The following register is located at an offset of zero from (GAME_PORT) the address into the base I/O address register for Logical Device 9. REG OFFSET NAME Game Port Register Default = 0x00 on VTR POR SMSC DS – LPC47M112 Table 59 - Game Port (hex) DESCRIPTION 00 Game Port Register Bit[0] ...
Page 156
... SYSTEM ELEMENTS Primary Configuration Address Decoder After a hard reset (nPCI_RESET pin asserted) or Vcc Power On Reset the LPC47M112 is in the Run Mode with all logical devices disabled. The logical devices may be configured through two standard Configuration I/O Ports (INDEX and DATA) by placing the LPC47M112 into Configuration Mode. ...
Page 157
... MOV DX,02FH MOV AL, 08H OUT DX,AL;Point to Logical Device 8 ; MOV DX,02EH MOV AL,E0H OUT DX,AL ; Point to CRE0 MOV DX,02fH MOV AL,02H OUT DX,AL ; Update CRE0 ;-----------------------------. ; EXIT CONFIGURATION MODE ;-----------------------------' MOV DX,02EH MOV AX,0AAH OUT DX,AL SMSC DS – LPC47M112 | | | | Page 157 DATASHEET Rev. 02-16-07 ...
Page 158
... Datasheet Notes: HARD RESET: nPCI_RESET pin asserted SOFT RESET: Bit 0 of Configuration Control register set to one All host accesses are blocked for 500µs after Vcc POR (see Power-up Timing Diagram) Table 60 – LPC47M112 Configuration Registers Summary HARD INDEX TYPE RESET ...
Page 159
... R/W 0x00, 0x61 0x00 0XF0 R/W - 0xF1 R - LOGICAL DEVICE B CONFIGURATION REGISTERS (MPU-401) 0x30 R/W 0x00 0x60, R/W 0x03 SMSC DS – LPC47M112 SOFT VCC POR VTR POR RESET 0x00 0x00 - 0x00 0x00 0x00 0x00, 0x00, 0x00, 0x00 0x00 0x00 0x00 0x00 ...
Page 160
... TYPE RESET 0x61 R/W 0x30 0x70 R/W 0x05 Note 1: CR22 bit 5 and bit 7 are reset on VTR only. Reserved registers are read-only, reads return 0. Note: SMSC DS – LPC47M112 SOFT VCC POR VTR POR RESET 0x30 0x30 0x30 0x05 0x05 0x05 Page 160 ...
Page 161
... R/W Default = 0x00 on VCC POR, VTR POR, SOFT RESET and HARD RESET SMSC DS – LPC47M112 Table 61 - Chip Level Registers DESCRIPTION Chip (Global) Control Registers Reserved - Writes are ignored, reads return 0. The hardware automatically clears this bit after the write, there is no need for software to clear the bits. ...
Page 162
... HARD RESET Chip Level 0x29 Vendor Defined TEST 6 0x2A R/W Default = 0x00, on VCC POR and VTR POR SMSC DS – LPC47M112 DESCRIPTION Bit[0] FDC Bit[1] Reserved Bit[2] Reserved Bit[3] Parallel Port Bit[4] Serial Port 1 Bit[5] Serial Port 2 Bit[6] Serial Port 3 Bit[7] Reserved (read as 0) ...
Page 163
... DATA PORT. The Logical Device registers are accessible only when the device is in the Configuration State. The logical register addresses are shown in the table below. SMSC DS – LPC47M112 DESCRIPTION Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results. ...
Page 164
... Memory Space (0x76-0xA8) Configuration Logical Device (0xA9-0xDF) Logical Device (0xE0-0xFE) Configuration Reserved SMSC DS – LPC47M112 Table 62 – Logical Device Registers ADDRESS DESCRIPTION (0x30) Bits[7:1] Reserved, set to zero. Bit[ Activates the logical device currently selected through the Logical Device # register Logical device currently selected is inactive Reserved – ...
Page 165
... Note 3: The default value of the Primary Interrupt Select register for logical device 0 is 0x06. Note 4: The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for logical device 3 and 5 is 0x04. SMSC DS – LPC47M112 Page 165 DATASHEET ...
Page 166
... Serial Port 1 0x05 Serial Port 2 0x06 Reserved 0x07 KYBD 0x08 Reserved 0x09 Game Port 0x0A Runtime Registers 0x0B MPU-401 SMSC DS – LPC47M112 BASE I/O REGISTER RANGE INDEX (NOTE 1) 0x60,0x61 [0x0100:0x0FF8 BYTE BOUNDARIES n/a n/a n/a n/a 0x60,0x61 [0x0100:0x0FFC BYTE BOUNDARIES (EPP Not supported) ...
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... Note: nSMI must be disabled to use IRQ2. Note: All IRQ’s are available in Serial IRQ mode. Note: Note 1: The default value of the Primary Interrupt Select register for logical device 0 is 0x06. SMSC DS – LPC47M112 BASE I/O REGISTER RANGE INDEX (NOTE 1) 0x26, 0x27 ...
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... ECR REGISTER) 000 001 010 011 100 101 110 111 d. Keyboard Controller: Refer to the KBD section of this spec. SMSC DS – LPC47M112 DEFINITION Bits[2:0] select the DMA Channel. 0x00= Reserved 0x01= DMA1 0x02= DMA2 0x03= DMA3 0x04-0x07= No DMA active IRQ PIN CONTROLLED BY PRINTER ...
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... Bit[7:4] Reserved. Bits[1:0] Floppy Drive A Type Bits[3:2] Floppy Drive B Type Bits[5:4] Reserved (could be used to store Floppy Drive C type) Bits[7:6] Reserved (could be used to store Floppy Drive D type) Note: The LPC47M112 supports two floppy drives Reserved, Read as 0 (read only) Page 169 DATASHEET STATE C C ...
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... HARD RESET 0xF1 R/W PP Mode Register 2 Default = 0x00 on VCC POR, VTR POR and HARD RESET SMSC DS – LPC47M112 DEFINITION Bits[1:0] Drive Type Select: DT1, DT0 Bits[2] Read as 0 (read only) Bits[4:3] Data Rate Table Select: DRT1, DRT0 Bits[5] Read as 0 (read only) ...
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... Table 68 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] NAME REG INDEX Serial Port 2 0xF0 R/W Mode Register Default = 0x00 on VCC POR, VTR POR and HARD RESET SMSC DS – LPC47M112 DEFINITION Bit[0] MIDI Mode = 0 MIDI support disabled (default MIDI support enabled Bit[1] High Speed = 0 High Speed Disabled(default) ...
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... Note 1: The TXD2_MODE bit is a VTR powered bit that is reset on VTR POR only. Table 69 - KYBD, Logical Device 7 [Logical Device Number = 0x07] NAME REG INDEX KRST_GA20 0xF0 R/W Default = 0x00 on VCC POR, VTR POR and HARD RESET SMSC DS – LPC47M112 DEFINITION Bit[0] Receive Polarity = 0 Active High (Default Active Low Bit[1] Transmit Polarity = 0 Active High = 1 ...
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... MPU-401 Primary 0x61 R/W Base I/O Address Low Byte Default = 0x30 on HARD RESET, SOFT RESET, VCC POR and VTR POR SMSC DS – LPC47M112 DEFINITION Bit[0] Reserved Reserved - read as ‘0’ Table 70 - PME, Logical Device A DEFINITION Bit[0] (CLK32_PRSN) 0=32kHz clock is connected to the CLKI32 ...
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... High Input Leakage IO6 Type Buffer Low Output Level High Output Level Output Leakage OD6 Type Buffer Low Output Level Output Leakage O6 Type Buffer Low Output Level High Output Level SMSC DS – LPC47M112 SYMBOL MIN TYP MAX V 0.8 ILI V 2.0 IHI V 0 ...
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... Output Leakage OP14 Type Buffer Low Output Level High Output Level Output Leakage IOP14 Type Buffer Low Output Level High Output Level Output Leakage IOD16 Type Buffer Low Output Level Output Leakage SMSC DS – LPC47M112 SYMBOL MIN TYP MAX -10 ...
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... CIR ‘on’ mA. TRI and CIR ‘off’ is 250 μA. Note 5: Min I with V TRI CC CAPACITANCE T = 25° 1MHz PARAMETER SYMBOL Clock Input Capacitance Input Capacitance Output Capacitance C SMSC DS – LPC47M112 SYMBOL MIN TYP MAX I ± ± ± CCI ...
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... Enhanced Super I/O Controller with LPC Interface Datasheet 31 TIMING DIAGRAMS For the Timing Diagrams shown, the following capacitive loads are used on outputs. SMSC DS – LPC47M112 CAPACITANCE NAME TOTAL (pF) SER_IRQ 50 nLAD[3:0] 50 nLDRQ 50 nDIR 240 nSTEP 240 nDS0-1 240 nWDATA 240 PD[0:7] 240 ...
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... Clock Cycle Time for 14.318MHz t2 Clock High Time/Low Time for 14.318MHz t1 Clock Cycle Time for 32kHz t2 Clock High Time/Low Time for 32kHz Clock Rise Time/Fall Time (not shown) SMSC DS – LPC47M112 t 1 FIGURE 8 - POWER-UP TIMING MIN 300 100 125 t1 t2 FIGURE 9A - INPUT CLOCK TIMING ...
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... Rise Time t5 Fall Time nPCI_RESET NAME t4 nPCI_RESET width (Note 1) Note 1: The nPCI_RESET width is dependent upon the processor clock. The nPCI_RESET must be active while the clock is running and stable. SMSC DS – LPC47M112 FIGURE 9B – PCI CLOCK TIMING DESCRIPTION t4 FIGURE 9C - RESET TIMING DESCRIPTION ...
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... Float to Active Delay t3 Active to Float Delay CLK Input FIGURE 11 – INPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS NAME t1 Input Set Up Time to CLK – Bused Signals t2 Input Hold Time from CLK SMSC DS – LPC47M112 t1 t2 DESCRIPTION t1 Inputs Valid DESCRIPTION Page 180 DATASHEET t3 MIN ...
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... Enhanced Super I/O Controller with LPC Interface Datasheet PCI_CLK nLFRAME nLAD[3: Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 PCI_CLK nLFRAME nLAD[3: Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 SMSC DS – LPC47M112 Address Data TAR Sync=0110 FIGURE 12 – I/O WRITE Address TAR Sync=0110 FIGURE 13 – I/O READ Page 181 DATASHEET L3 TAR ...
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... Start C+D CHL Size nLAD[3:0] Note: L1=Sync of 0000 PCI_CLK nLFRAME nLAD[3:0] Start C+D CHL Size Note: L1= Sync of 0000 SMSC DS – LPC47M112 MSB LSB TAR Sync=0101 FIGURE 15 – DMA WRITE (FIRST BYTE) Data TAR Sync=0101 FIGURE 16 – DMA READ (FIRST BYTE) ...
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... Setup Time nDIR Low (Note) *X specifies one MCLK period and Y specifies one WCLK period. MCLK = 16 x Data Rate (at 500 kb/s MCLK = 8 MHz) WCLK = 2 x Data Rate (at 500 kb/s WCLK = 1 MHz) Note: The nDS0-1 setup and hold times must be met by software. SMSC DS – LPC47M112 ...
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... Deasserted to Command Deasserted (Note 1) t8 Command Asserted to nWAIT Deasserted t9 Command Deasserted to nWAIT Asserted Note 1: nWAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is considered to have settled after it does not transition for a minimum of 50 nsec. SMSC DS – LPC47M112 DESCRIPTION Page 184 DATASHEET ...
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... Deasserted to Command Deasserted (Note 1) t11 PDATA Valid to nWAIT Deasserted t12 PDATA Hi-Z to nWAIT Asserted Note 1: nWAIT is considered to have settled after it does not transition for a minimum of 50 ns. Note 2: When not executing a write cycle, EPP nWRITE is inactive high. SMSC DS – LPC47M112 t11 ...
Page 186
... FIGURE 20 – EPP 1.7 DATA OR ADDRESS WRITE CYCLE NAME t1 Command Deasserted to nWRITE Change t2 Command Deasserted to PDATA Invalid t3 PDATA Valid to Command Asserted t4 nWRITE to Command t5 Command Deasserted to nWAIT Deasserted SMSC DS – LPC47M112 t3 t4 DESCRIPTION Page 186 DATASHEET MIN TYP MAX UNITS 0 ...
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... Enhanced Super I/O Controller with LPC Interface Datasheet nWRITE PD<7:0> nDATASTB nADDRSTB nWAIT FIGURE 21 – EPP 1.7 DATA OR ADDRESS READ CYCLE NAME t1 Command Asserted to PDATA Valid t2 Command Deasserted to PDATA Hi-Z t3 Command Deasserted to nWAIT Deasserted SMSC DS – LPC47M112 t1 DESCRIPTION Page 187 DATASHEET t2 t3 MIN TYP MAX UNITS ...
Page 188
... HostAck (nALF) high to acknowledge the handshake. The peripheral then sets PeriphClk (nACK) high. After the host has accepted the data it sets HostAck (nALF) low, completing the transfer. This sequence is shown in Figure 24. SMSC DS – LPC47M112 Page 188 DATASHEET Rev. 02-16-07 ...
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... BUSY Inactive to nSTROBE Active t6 BUSY Inactive to PDATA Invalid (Note 1) Note 1: The data is held until BUSY goes inactive or for time t3, whichever is longer. This only applies if another data transfer is pending other data transfer is pending, the data is held indefinitely. SMSC DS – LPC47M112 DESCRIPTION Page 189 ...
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... Deasserted to Busy Deasserted t7 BUSY Deasserted to nSTROBE Asserted (Notes 1,2) t8 BUSY Asserted to nSTROBE Deasserted (Note 2) Note 1: Maximum value only applies if there is data in the FIFO waiting to be written out. Note 2: BUSY is not considered asserted or deasserted until it is stable for a minimum 130 ns. SMSC DS – LPC47M112 ...
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... Deasserted to nACK Deasserted Note 1: Maximum value only applies if there is room in the FIFO and terminal count has not been received. ECP can stall by keeping nALF low. Note 2: nACK is not considered asserted or deasserted until it is stable for a minimum 130 ns. SMSC DS – LPC47M112 ...
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... Bit Time at 19.2kba 9.6kba 4.8kba 2.4kba Recei ve Pu lse Detection ria ceived p ulse is consi dered d etecte d if the receive d p ulse is a mini mum o f 1.41µ RX: L5, CRF1 Bit nIRRX: L5, CRF1 (defaul t) SMSC DS – LPC47M112 min ty p 1.4 1.6 1.4 3.22 1 ...
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... Bit Tim e at 9.6kbaud t2 Bit Tim e at 4.8kbaud t2 Bit Tim e at 2.4kbaud Notes: 1. IrDA @ 115k i s HPSIR compati ble. IrDA @ 2400 low compatibility with HP95LX and 48SX. 2. IRT X: L5, CRF 1 Bit (default) nIRT X: L5, CRF1 Bit SMSC DS – LPC47M112 min Parameter typ 1.41 1 ...
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... M odu lated Outp ut " On" odu lated Out put " Off" Note IRRX CRF 1 Bit IRRX CRF 1 Bit (de fault) M IRRX, nMI RRX are the mod ulate d ou tpu ts FIGURE 27 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING SMSC DS – LPC47M112 ramet er min typ max 0 ...
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... M odu lated Outp ut " On" odu lated Outp ut " Off" Note IRTX : L5 , CRF 1 Bit (def ault) nI RTX CRF1 Bit MIRTX, nM IRTX a re the mod ulate d ou tpu ts FIGURE 28 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING SMSC DS – LPC47M112 ramet er min ...
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... Serial Port Data Bit Time Note 1/Baud Rate. The Baud Rate is programmed through the divisor latch registers. Baud Rates have BR percentage errors indicated in the “Baud Rate” table in the “Serial Port” section. SMSC DS – LPC47M112 t1 FIGURE 29 – SETUP AND HOLD TIME MIN 7 ...
Page 197
... Enhanced Super I/O Controller with LPC Interface Datasheet J1X, J1Y, J2X, J2Y FIGURE 31 – JOYSTICK POSITION SIGNAL NAME t1 Rise Time to 2/3 VREF J1B1, J1B2, J2B1, J2B2 NAME t1, t2 Button Fall/Rise Time SMSC DS – LPC47M112 t1 DESCRIPTION 90% 10% t1 FIGURE 32 – JOYSTICK BUTTON SIGNAL DESCRIPTION Page 197 DATASHEET VREF 2 VREF +/- 5% ...
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... Duration of CLOCK active (Receive/Send) t5 Time to keyboard inhibit after clock 11 to ensure the keyboard does not start another transmission (Receive) t6 Time from inactive to active CLOCK transition, used to time when the auxiliary device samples DATA (Send) SMSC DS – LPC47M112 CLK 2 9 Bit 7 Parity Bit DESCRIPTION ...
Page 199
... Note 2: When Bit 0 of the FANx registers is 0, then the duty cycle is programmed through Bits[6:1] of these registers. If Bits[6:1] = “000000” then the FANx pin is low. The duty cycle is programmable through Bits[6: between 1.56% and 98.44%. When Bit the FANx pin is high. SMSC DS – LPC47M112 t1 Data Data FIGURE 34– ...
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... Note 1: The blink rate is programmed through Bits[1:0] in LEDx register. When Bits[1:0]=00, LED is OFF. Bits[1:0]=01 indicates LED blink at 1Hz rate with a 50% duty cycle (0.5 sec ON, 0.5 sec OFF). Bits[1:0]=10 indicates LED blink at ½ Hz rate with a 25% duty cycle (0.5 sec ON, 1.5 sec OFF). When Bits[1:0]=11, LED is ON. SMSC DS – LPC47M112 ...