LPC47M112-MW Standard Microsystems (SMSC), LPC47M112-MW Datasheet - Page 111

• Manufacturer Part Number: LPC47M112-MW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M112-MW

• Lead Free Status / RoHS Status: Compliant

Enhanced Super I/O Controller with LPC Interface
Datasheet
Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode compatible
software. This signal is externally OR’ed with the A20GATE signal from the keyboard controller and CPURST to
control the nA20M input of the CPU. Writing a 0 to bit 1 of the Port 92 Register forces ALT_A20 low. ALT_A20 low
drives nA20M to the CPU low, if A20GATE from the keyboard controller is also low. Writing a 1 to bit 1 of the Port 92
Register forces ALT_A20 high. ALT_A20 high drives nA20M to the CPU high, regardless of the state of A20GATE
from the keyboard controller. Upon reset, this signal is driven low.
21.1
The implementation of the latches on the keyboard and mouse interrupts is shown below.
SMSC DS – LPC47M112
Latches On Keyboard and Mouse IRQs
Note: When Port 92 is disabled,
writes are ignored and reads
return undefined values.
P92
8042
Bit 0
P20
Pulse
Gen
14us
KRST_GA20
DATASHEET
Bit 2
6us
14us
Page 111
KRST
6us
nALT_RST
KBDRST
Rev. 02-16-07