ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 38
ISP1760ET,557
Manufacturer Part Number
ISP1760ET,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1760ET557.pdf
(111 pages)
Specifications of ISP1760ET,557
Package Type
TFBGA
Pin Count
128
Lead Free Status / RoHS Status
Compliant
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NXP Semiconductors
Table 25.
ISP1760_4
Product data sheet
Bit
31 to 0
ISO PTD Done Map register (address 0130h) bit description
Symbol
ISO_PTD_DONE
_MAP[31:0]
8.2.7 ISO PTD Done Map register
8.2.8 ISO PTD Skip Map register
Table 24.
[1]
[2]
The bit description of the register is given in
This register represents a direct map of the done status of the 32 PTDs. The bit
corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is
completed. Reading the Done Map register will clear all the bits that are set to logic 1, and
the next reading will reflect the updated status of new executed PTDs.
Table 26
Bit
31 to 20
19 to 16
15 to 14
13
12
11 to 10
9
8
7
6
5 to 3
2
1
0
For details on register bit description, refer to
Universal Serial Bus Rev.
These fields read logic 0, if the PP (Port Power) bit in register PORTSC1 is logic 0.
Access
R
shows the bit description of the register.
Symbol
-
PTC[3:0]
PIC[1:0]
PO
PP
LS[1:0]
-
PR
SUSP
FPR
-
PED
ECSC
ECCS
PORTSC1 - Port Status and Control 1 register (address 0064h) bit description
Value
0000 0000h
Description
reserved
Port Test Control: When this field is zero, the port is not operating in test
mode. A nonzero value indicates that it is operating in test mode indicated
by the value.
Port Indicator Control: Writing to this field has no effect if the
P_INDICATOR bit in the HCSPARAMS register is logic 0.
For a description on how these bits are implemented, refer to
“Universal Serial Bus Specification Rev.
Port Owner: This bit unconditionally goes to logic 0 when the configured
bit in the CONFIGFLAG register makes a logic 0 to logic 1 transition. This
bit unconditionally goes to logic 1 whenever the configured bit is logic 0.
Port Power: The function of this bit depends on the value of the PPC (Port
Power Control) field in the HCSPARAMS register.
Line Status: This field reflects the current logical levels of the DP (bit 11)
and DM (bit 10) signal lines.
reserved
Port Reset: Logic 1 means the port is in the reset state. Logic 0 means
the port is not in reset.
Suspend: Logic 1 means the port is in the suspend state. Logic 0 means
the port is not suspended.
Force Port Resume: Logic 1 means resume detected or driven on the
port. Logic 0 means no resume (K-state) detected or driven on the port.
reserved
Port Enabled/Disabled: Logic 1 means enable. Logic 0 means disable.
Connect Status Change: Logic 1 means change in ECCS. Logic 0
means no change.
Current Connect Status: Logic 1 indicates a device is present on the
port. Logic 0 indicates no device is present.
Rev. 04 — 4 February 2008
1.0”.
[1]
Description
ISO PTD Done Map: Done map for each of the 32 PTDs for
the ISO transfer
[2]
Ref. 2 “Enhanced Host Controller Interface Specification for
[2]
Table
[2]
Embedded Hi-Speed USB host controller
25.
2.0”.
[2]
[2]
© NXP B.V. 2008. All rights reserved.
ISP1760
Ref. 1
37 of 110
[2]
[2]
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