ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 28

• Manufacturer Part Number: ISP1760ET,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1760ET,557

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
ISP1760_4
Product data sheet
7.9 Power-On Reset (POR)
Table 6.
In hybrid mode (see
transistor, controlled using one of the GPIO pins of the processor. This helps to reduce the
suspend current, I
V
back on, before the resume programming sequence starts.
Table 7
Table 7.
When V
t
1.2 V.
Voltage
V
V
Pins
DATA[31:0], A[17:1], TEST1, TEST2, TEST3,
TEST4, TEST5, TEST6, TEST7, DREQ,
DACK, IRQ, SUSPEND/WAKEUP_N
CS_N, RESET_N, RD_N, WR_N
PORP
Fig 10. Hybrid mode
CC(5V0)
CC(5V0)
CC(I/O)
, will typically be 800 ns. The pulse is started when V
shows the status of output pins during hybrid mode.
CC(I/O)
is off during suspend, a 2 ms reset pulse is required when power is switched
The figure shows the LQFP pinout. For the TFBGA ballout, see
A 4.7 F-to-10 F electrolytic or tantalum capacitor is required on any one of the pins 5, 50 or 118.
All the electrolytic or tantalum capacitors must be of LOW ESR type (0.2
Hybrid mode
Pin status in hybrid mode
is directly connected to the RESET_N pin, the internal POR pulse width,
CC(I/O)
Figure
Rev. 04 — 4 February 2008
, below 100 A. If the ISP1760 is used in hybrid mode and
ISP1760BE
10, 40, 48,
59, 67, 75,
5, 50, 118
10), V
104, 115
83, 94,
6, 7
85
9
CC(5V0)
V
V
REG1V8
REG1V8
REG3V3
CC(5V0)
CC(I/O)
10 µF
can be switched off using an external PMOS
controlled by the CPU
V
on
on
off
on
off
CC(I/O)
Embedded Hi-Speed USB host controller
10 µF
Status
off
on
100 nF
100 nF
004aaa677
100 nF
1.65 V to 3.6 V
100 nF
3.3 V to 5 V
V
on
off
X
X
X
CC(5V0)
100 nF
CC(5V0)
Table
2.
rises above V
to 2 ).
© NXP B.V. 2008. All rights reserved.
ISP1760
Status
normal
high-Z
undefined
input
undefined
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