W83627THF Nuvoton Technology Corporation of America, W83627THF Datasheet - Page 97

• Manufacturer Part Number: W83627THF
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627THF

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

7.1.6
CR30 (Default 0x00)
CR60, CR 61 (Default 0x02, 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)
These two registers select the Game Port base address [0x100:0xFFF] on 1 byte boundary.
CR62, CR 63 (Default 0x03, 0x30 if PNPCSV = 0 during POR, default 0x00 otherwise)
These two registers select the MIDI Port base address [0x100:0xFFF] on 2 byte boundary.
CR70 (Default 0x09 if PNPCSV = 0 during POR, default 0x00 otherwise)
CRF0 (GP1[7:0] I/O selection register. Default 0xFF)
When set to a '1', respective GPIO port is programmed as an input port.
When set to a '0', respective GPIO port is programmed as an output port.
CRF1 (GP1[7:0] data register. Default 0x00)
If a port is programmed to be an output port, then its respective bit can be read/written.
If a port is programmed to be an input port, then its respective bit can only be read.
CRF2 (GP1[7:0] inversion register. Default 0x00)
When set to a '1', the incoming/outgoing port value is inverted.
When set to a '0', the incoming/outgoing port value is the same as in data register.
Bit 7 - 4 : Reserved.
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7 - 4 : Reserved.
Bit [3:0] : These bits select IRQ resource for MIDI Port .
Logical Device 7 (Game Port and MIDI Port and GPIO Port 1 and 5)
= 1 Enable GPIO port 5.
= 0 Disable GPIO port 5.
= 1 Enable MIDI Port.
= 0 MIDI Port is disabled if bit 0 of this register is also 0.
= 1 Enable game Port.
= 0 Game Port is disabled if bit 0 of this register is also 0.
= 1 Enable GPIO port 1, game Port and MIDI Port.
= 0 Disable GPIO port 1. Game Port and MIDI Port are enabled/disabled by bit 1 and 2 of
this register respectively.
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W83627THF/W83627THG