W83627THF Nuvoton Technology Corporation of America, W83627THF Datasheet - Page 89

• Manufacturer Part Number: W83627THF
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627THF

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

CR70 (Default 0x06 if PNPCSV = 0 during POR, default 0x00 otherwise)
CR74 (Default 0x02 if PNPCSV = 0 during POR, default 0x04 otherwise)
CRF0 (Default 0x0E)
FDD Mode Register
Bit 7 - 4 : Reserved.
Bit 3 - 0 : These bits select IRQ resource for FDC.
Bit 7 - 3 : Reserved.
Bit 2 - 0 : These bits select DRQ resource for FDC.
Bit 7
This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0,
DSKCHG, and WP.
Bit 6
This bit determines the polarity of all FDD interface signals.
Bit 5
When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A.
Bit 4
Bit 3 - 2 :Interface Mode
Bit 1
Bit 0
= 0x00 DMA0
= 0x01 DMA1
= 0x02 DMA2
= 0x03 DMA3
= 0x04 - 0x07 No DMA active
: FIPURDWN
= 0 The internal pull-up resistors of FDC are turned on.(Default)
= 1 The internal pull-up resistors of FDC are turned off.
: INTVERTZ
= 0 FDD interface signals are active low.
= 1 FDD interface signals are active high.
: DRV2EN (PS2 mode only)
: Swap Drive 0, 1 Mode
= 0 No Swap (Default)
= 1 Drive and Motor select 0 and 1 are swapped.
= 11 AT Mode (Default)
= 10 (Reserved)
= 01 PS/2
= 00 Model 30
: FDC DMA Mode
= 0 Burst Mode is enabled
= 1 Non-Burst Mode (Default)
: Floppy Mode
= 0 Normal Floppy Mode (Default)
= 1 Enhanced 3-mode FDD
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W83627THF/W83627THG