HCPL-0708-500 Avago Technologies US Inc., HCPL-0708-500 Datasheet - Page 11

• Manufacturer Part Number: HCPL-0708-500
• Manufacturer: Avago Technologies US Inc.

Specifications of HCPL-0708-500

• Number Of Elements: 1
• Input Type: DC
• Forward Voltage: 1.8V
• Forward Current: 20mA
• Output Current: 2mA
• Package Type: SOIC
• Operating Temp Range: -40C to 100C
• Propagation Delay Time: 60ns
• Pin Count: 8
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Output Type: Push-Pull
• Isolation Voltage: 3750Vrms
• Lead Free Status / RoHS Status: Not Compliant

Pulse-width distortion (PWD) is the difference between
t
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by the
minimum pulse width (in ns) being transmitted. Typical-
ly, PWD on the order of 20 - 30% of the minimum pulse
width is tolerable; the exact figure depends on the par-
ticular application.
Propagation delay skew, t
to consider in parallel data applications where synchro-
nization of signals on parallel data lines is a concern. If
the parallel data is being sent through a group of opto-
couplers, differences in propagation delays will cause the
data to arrive at the outputs of the optocouplers at differ-
ent times. If this difference in propagation delay is large
enough it will determine the maximum rate at which
parallel data can be sent through the optocouplers.
V
V
Figure 9. Propagation delay skew waveform.
Propagation delay skew represents the uncertainty of
where an edge might be after being sent through an op-
tocoupler. Figure 10 shows that there will be uncertainty
in both the data and clock lines. It is important that these
two areas of uncertainty not overlap, otherwise the clock
signal might arrive before all of the data outputs have
settled, or some of the data outputs may start to change
before the clock signal has arrived. From these consider-
ations, the absolute minimum pulse width that can be sent
PHL
I
I
O
O
F
F
and t
PLH
50%
50%
CMOS
and often determines the maximum data
2.5 V,
t
PSK
PSK
, is an important parameter
2.5 V,
CMOS
Propagation delay skew is defined as the difference be-
tween the minimum and maximum propagation delays,
either t
which are operating under the same conditions (i.e., the
same drive current, supply voltage, output load, and op-
erating temperature). As illustrated in Figure 9, if the in-
puts of a group of optocouplers are switched either ON
or OFF at the same time, t
the shortest propagation delay, either t
the longest propagation delay, either t
As mentioned earlier, t
parallel data transmission rate. Figure 10 is the timing
diagram of a typical parallel data application with both
the clock and data lines being sent through the opto-
couplers. The figure shows data and clock signals at the
inputs and outputs of the optocouplers. In this case the
data is assumed to be clocked off of the rising edge of
the clock.
INPUTS
OUTPUTS
through optocouplers in a parallel application is twice t
A cautious design should use a slightly longer pulse
width to ensure that any additional uncertainty in the
rest of the circuit does not cause a problem.
The HCPL-0708 optocouplers offer the advantage of
guaranteed specifications for propagation delays, pulse-
width distortion, and propagation delay skew over the
recommended temperature and power supply ranges.
Figure 10. Parallel data transmission example.
CLOCK
CLOCK
DATA
DATA
PLH
or t
PHL
t
PSK
, for any given group of optocouplers
PSK
t
PSK
PSK
can determine the maximum
is the difference between
PLH
PLH
or t
or t
PHL
PHL
.
, and
PSK
.