CY7C185-35LMB Cypress Semiconductor Corp, CY7C185-35LMB Datasheet - Page 4

• Manufacturer Part Number: CY7C185-35LMB
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C185-35LMB

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-05043 Rev. *B
Switching Waveforms
Read Cycle No.1
Read Cycle No.2
Notes:
10. Data I/O is High Z if OE = V
11. The internal write time of the memory is defined by the overlap of CE
8. Device is continuously selected. OE, CE
9. WE is HIGH for read cycle.
DATA OUT
DATA OUT
CURRENT
ADDRESS
to initiate write. A write can be terminated by CE
rising edge of the signal that terminates the write.
SUPPLY
CE
CE
V
OE
OE
CC
1
2
[8,9]
[10,11]
PREVIOUS DATA VALID
HIGH IMPEDANCE
IH
, CE
t
PU
1
t
= V
LZCE
IH
1
, WE = V
= V
t
t
LZOE
ACE
IL
. CE
t
50%
OHA
1
t
DOE
IL
or WE going HIGH or CE
2
, or CE
= V
IH
.
2
=V
t
AA
IL
.
t
RC
1
LOW, CE
2
going LOW. The data input set-up and hold timing should be referenced to the
t
RC
2
HIGH and WE LOW. CE
DATA VALID
1
and WE must be LOW and CE
t
DATA VALID
HZOE
t
HZCE
t
PD
50%
CY7C185
IMPEDANCE
2
must be HIGH
Page 4 of 12
HIGH
ICC
ISB
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