CY7C185-25VI Cypress Semiconductor Corp, CY7C185-25VI Datasheet
CY7C185-25VI
Specifications of CY7C185-25VI
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CY7C185-25VI Summary of contents
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... CMOS for optimum speed/power • Easy memory expansion with CE • TTL-compatible inputs and outputs • Automatic power-down when deselected [1] Functional Description The CY7C185 is a high-performance CMOS static RAM orga- nized as 8192 words by 8 bits. Easy memory expansion is Logic Block Diagram INPUT BUFFER A 1 ...
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... CC Output Disabled V = Max GND OUT V = Max OUT Max Min. Duty Cycle = 100% Max – 0.3V 0. – CY7C185 Ambient Temperature + 10% – + 10% 7C185-15 7C185-20 Min. Max. Min. Max. Unit 2.4 2.4 V 0.4 0 0.3V 0.3V –0.5 0.8 –0.5 0.8 V –5 +5 –5 +5 – ...
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... Min. Duty Cycle = 100% Max – – Test Conditions MHz 5. 481 255 INCLUDING JIGAND SCOPE (b) 1.73V CY7C185 7C185-25 7C185-35 Min. Max. Min. Max. 2.4 2.4 0.4 0 0.3V 0.3V –0.5 0.8 –0.5 0.8 –5 +5 –5 +5 –5 +5 –5 +5 –300 –300 100 ...
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... AC Test Loads. Transition is measured 500 mV from steady state voltage less than t and t for any given device. HZCE LZCE1 LZCE2 LOW, CE HIGH, and WE LOW. All 3 signals must be active to initiate a write and either 1 2 CY7C185 7C185-25 7C185-35 Max. Min. Max. Min. Max ...
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... LOW, CE HIGH and WE LOW going HIGH or CE going LOW. The data input set-up and hold timing should be referenced to the 1 2 DATA VALID t HZOE t HZCE DATA VALID VALID and WE must be LOW and CE 1 CY7C185 HIGH IMPEDANCE ICC ISB must be HIGH 2 Page ...
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... The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state Document #: 38-05043 Rev SCE1 SCE2 t AW DATA [13,14,15,16 SCE1 t SCE2 t AW DATA HZWE VALID VALID IN t LZWE and t . HZWE SD CY7C185 Page ...
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... OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 = 125 0.0 1.0 2.0 OUTPUT VOLTAGE (V) NORMALIZED I vs. CYCLE TIME CC 1.25 V =5. = =0.5V CC 1.00 0.75 0.50 1000 CYCLE FREQUENCY (MHz) CY7C185 =5.0V =25 C 3.0 4.0 =5.0V 3.0 4.0 40 Page ...
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... A9 Y1 A10 Y4 A11 Y3 A12 Ordering Information Speed (ns) Ordering Code 15 CY7C185-15PC CY7C185-15SC CY7C185-15VC CY7C185-15VI 20 CY7C185-20PC CY7C185-20SC CY7C185-20VC CY7C185-20VI 25 CY7C185-25PC CY7C185-25SC CY7C185-25VC CY7C185-25VI 35 CY7C185-35PC CY7C185-35SC CY7C185-35VC CY7C185-35VI Document #: 38-05043 Rev Input/Output X High Z X High Z L Data Out X Data In H High Package Name Package Type ...
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... Package Diagrams Document #: 38-05043 Rev. *A 28-Lead (300-Mil) Molded DIP P21 28-Lead (300-Mil) Molded SOIC S21 CY7C185 51-85014-*B 51-85026-*A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 28-Lead (300-Mil) Molded SOJ V21 CY7C185 51-85031-*B Page ...
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... Document History Page Document Title: CY7C185 Static RAM Document Number: 38-05043 Issue REV. ECN NO. Date ** 107145 09/10/01 *A 116470 09/16/02 Document #: 38-05043 Rev. *A Orig. of Change Description of Change SZV Change from Spec number: 38-00037 to 38-05043 CEA Add applications foot note to data sheet. CY7C185 ...