STK12C68-5C45M Cypress Semiconductor Corp, STK12C68-5C45M Datasheet - Page 9

• Manufacturer Part Number: STK12C68-5C45M
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK12C68-5C45M

• Word Size: 8b
• Organization: 8Kx8
• Density: 64Kb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 5V
• Package Type: CDIP
• Operating Temperature Classification: Military
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: -55C to 125C
• Pin Count: 28
• Mounting: Through Hole
• Supply Current: 80mA
• Lead Free Status / RoHS Status: Not Compliant

WRITE
STORE
circuitry and no
still be disabled until HSB is allowed to return
Software initiated
less of whether or not a
place.
PREVENTING AUTOMATIC STORES
The AutoStore ™ function can be disabled on the fly by
holding HSB
15mA at a VOH of at least 2.2V as it will have to
overpower the internal pull-down device that drives
HSB low for 50ns at the onset of an AutoStore ™.
When the STK12C68-M is connected for
AutoStore ™operation (system V
and a 100uF capacitor on V
V
to pull HSB
the part will stop trying to pull HSB
AutoStore ™attempt.
LOW AVERAGE ACTIVE POWER
The STK12C68-M has been designed to draw signifi-
cantly less power when E is
100uF
± 20%
SWITCH
operation has taken place since the most recent
cycle. Note that if HSB is driven low via external
+
on the way down, the STK12C68 will attempt
LOW
Bypass
0.1uF
Schematic Diagram
HIGH
WRITE
; if HSB doesn't actually get below V
V
STORE
V
CAP
Figure 1
SS
with a driver capable of sourcing
1
14
s have taken place, the part will
nvSRAM
cycles are performed regard-
WRITE
LOW
28
26
CAP
V
HSB
CCX
CC
(chip enabled) but the
operation has taken
) and V
connected to V
LOW
10K Ohms
(optional)
Supply
Power
and abort the
CC
crosses
HIGH
100
CCX
80
60
40
20
0
IL
4-61
.
,
access cycle time is longer than 55ns. Figure 2 below
shows the relationship between I
for
cycle, and current consumption is given for all inputs at
CMOS
ship for
consumes only standby currents, and these plots do
not apply.
The cycle time used in Figure 2 corresponds to the
length of time from the later of the last address transi-
tion or E going
next address transition. W is assumed to be
while the state of G does not matter. Additional current
is consumed when the address lines change state
while E is asserted. The cycle time used in Figure 3
corresponds to the length of time from the later of W or
E going
The overall average current drawn by the part depends
on the following items: 1)
the time during which the chip is disabled (E
the cycle time for accesses (E
reads to writes; 5) the operating temperature; 6) the
V
50
I
CC
CC
Cycle Time (ns)
READ
100
(Max) Reads
Figure 2
level; and 7) output load.
or TTL levels. Figure 3 shows the same relation-
LOW
WRITE
150
cycles. All remaining inputs are assumed to
CMOS
TTL
to the earlier of W or E going
200
LOW
Note: Typical at 25 C
cycles. When E is
to the earlier of E going
CMOS
100
80
60
40
20
0
LOW
or TTL input levels; 2)
CC
50
and access times
); 4) the ratio of
I
Cycle Time (ns)
CC
HIGH
STK12C68-M
100
(Max) Writes
Figure 3
HIGH
, the chip
HIGH
HIGH
150
CMOS
TTL
or the
HIGH
.
); 3)
200
,