STK12C68-5C45M Cypress Semiconductor Corp, STK12C68-5C45M Datasheet - Page 7

• Manufacturer Part Number: STK12C68-5C45M
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK12C68-5C45M

• Word Size: 8b
• Organization: 8Kx8
• Density: 64Kb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 5V
• Package Type: CDIP
• Operating Temperature Classification: Military
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: -55C to 125C
• Pin Count: 28
• Mounting: Through Hole
• Supply Current: 80mA
• Lead Free Status / RoHS Status: Not Compliant

The STK12C68-M has two separate modes of opera-
tion:
mode, the memory operates as a standard fast static
RAM
SRAM
EEPROM
SRAM
STORE
software sequence or HSB assertion and are also
automatically initiated when the power supply voltage
level of the chip falls below V
tions are automatically initiated upon power-up and
whenever the power supply voltage level rises above
V
software sequence.
SRAM READ
The STK12C68-M performs a
and G are
specified on pins A
data bytes will be accessed. When the
by an address transition, the outputs will be valid after
a delay of t
outputs will be valid at t
later. The data outputs will repeatedly respond to
address changes within the t
the need for transitions on any control input pins, and
will remain valid until another address change or until
E or G is brought
SRAM WRITE
A write cycle is performed whenever E and W are
and HSB is high
to entering the
until either E or W go
data on pins DQ
is valid t
or t
It is recommended that G be kept
WRITE
common I/O lines. If G is left
turn off the output buffers t
SOFTWARE STORE
The STK12C68-M software
executing sequential
SWITCH
DVEH
. In nonvolatile mode, data is transferred from
SRAM
functions are disabled.
to
cycles may be initiated under user control via a
DVWH
cycle to avoid data bus contention on the
.
to
before the end of an E controlled
LOW
EEPROM
AVQV
RECALL
SRAM
mode and nonvolatile mode. In
. The address inputs must be stable prior
before the end of a W controlled
and HSB and W are
WRITE
. If the
0-7
(the
HIGH
0-12
cycles may also be initiated by a
will be written into the memory if it
HIGH
(the
RECALL
READ
READ
ELQV
cycle and must remain stable
determines which of the 8192
or W or HSB is brought
STORE
at the end of the cycle. The
WLQZ
STORE
AVQV
LOW
or at t
SWITCH
cycles from six specific
is initiated by E or G, the
READ
operation). In this mode
HIGH
after W goes
, internal circuitry will
access time without
operation) or from
HIGH
GLQV
cycle is initiated by
cycle whenever E
.
during the entire
READ
RECALL
. The address
, whichever is
DEVICE OPERATION
WRITE
is initiated
LOW
opera-
WRITE
SRAM
LOW
LOW
4-59
.
.
.
address locations. By relying on
STK12C68-M implements nonvolatile operation while
remaining compatible with standard 8Kx8 SRAMs.
During the
nonvolatile data is first performed, followed by a pro-
gram of the nonvolatile elements. The program opera-
tion copies the
ments. Once a
and output are disabled until the cycle is completed.
Because a sequence of addresses is used for
initiation, it is critical that no other read or write ac-
cesses intervene in the sequence or the sequence will
be aborted.
To initiate the
quence must be performed:
Once the sixth address in the sequence has been
entered, the
will be disabled. It is important that
not
is not necessary that G be
valid. After the t
SRAM
operation.
SOFTWARE RECALL
A
initiated with a sequence of
manner similar to the
RECALL
tions must be performed:
Internally,
SRAM data is cleared and second, the nonvolatile
information is transferred into the
RECALL
RECALL
1.
2.
3.
4.
5.
6.
2.
3.
4.
5.
6.
1.
WRITE
Read address
Read address
Read address
Read address
Read address
Read address
Read address
Read address
Read address
Read address
Read address
Read address
will again be activated for
cycle the following sequence of
operation in no way alters the data in the
RECALL
cycles be used in the sequence, although it
cycle of the
STORE
STORE
STORE
STORE
STORE
SRAM
is a two step procedure. First, the
cycle will commence and the chip
cycle, an erase of the previous
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0F (hex)
0000(hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0E (hex)
STORE
cycle time has been fulfilled, the
EEPROM
cycle the following
data into the nonvolatile ele-
cycle is initiated, further input
LOW
initiation. To initiate the
READ
for the sequence to be
READ
data into the
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE Cycle
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL Cycle
READ
SRAM
STK12C68-M
READ
operations in a
cycles only, the
READ
and
cells. The
cycles and
READ
SRAM
STORE
opera-
WRITE
se-
is