MR4A16BMA35 EverSpin Technologies Inc, MR4A16BMA35 Datasheet

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FEATURES • +3.3 Volt power supply • Fast 35 ns read/write cycle • SRAM compatible timing • Unlimited read & write endurance • Data always non-volatile for >20-years at temperature • RoHS-compliant small footprint BGA and TSOP package BENEFITS • One memory replaces FLASH, SRAM, EEPROM and BBSRAM in systems for simpler, more efficient designs • Improves reliability by replacing battery-backed SRAM INTRODUCTION The MR4A16B is a 16,777,216-bit magnetoresistive random access memory (MRAM) device organized as 1,048,576 words of 16 bits. The MR4A16B offers SRAM compatible 35 ns read/write timing with unlimited endurance. Data is always non-volatile for greater than 20-years. Data is automatically protected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification. To simplify fault tolerant design, MR4A16B includes internal single bit error correction code with 7 ECC parity bits for every 64 data bits. The MR4A16B is the ideal memory solution for applications that must permanently store and retrieve critical data and programs quickly. The MR4A16B is available in small footprint 48-pin ball grid array (BGA) package and a 54-pin thin small outline package (TSOPII). These packages are compatible with similar low-power SRAM products and other nonvolatile RAM products. The MR4A16B provides highly reliable data storage over a wide range of temperatures. The product is of- fered with commercial temperature (0 to +70 °C), industrial temperature (-40 to +85 °C), and automotive temperature (-40 to +125 °C) range options. CONTENTS 1. DEVICE PIN ASSIGNMENT......................................................................... 3 2. ELECTRICAL SPECIFICATIONS................................................................. 4 3. TIMING SPECIFICATIONS.......................................................................... ...

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DEVICE PIN ASSIGNMENT OUTPUT G ENABLE BUFFER 10 A[19:0] ADDRESS 10 BUFFER 20 CHIP E ENABLE BUFFER WRITE W ENABLE BUFFER UB UB BYTE ENABLE LB LB BUFFER Signal Name Function A Address Input E Chip Enable W Write Enable G Output Enable ...

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DEVICE PIN ASSIGNMENT Figure 1.2 Pin Diagrams for Available Packages (Top View DQU8 A5 DQU9 DQU10 V A17 DQU11 DQU12 DD A14 DQU14 DQU13 NC A12 DQU15 A18 A8 ...

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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field greater than the maximum field intensity specified in the maximum ratings. Parameter Supply voltage 2 Voltage on an pin 2 Output current per pin Package power dissipation Temperature under bias MR4A16B (Commercial) MR4A16BC (Industrial) MR4A16BM (Automotive) Storage Temperature Lead temperature during solder (3 minute max) Maximum magnetic field during write MR4A16B (All Temperatures) Maximum magnetic field during read or standby Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera- 1 tion should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. All voltages are referenced than 0.5V. The AC value less than 20mA. Power dissipation capability depends on package characteristics and use environment. 3 Everspin Technologies © 2010 ...

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Electrical Specifications Parameter Power supply voltage Write inhibit voltage Input high voltage Input low voltage Temperature under bias MR4A16B (Commercial) MR4A16BC (Industrial) MR4A16BM (Automotive) There startup time once (max 0 (max (min (min) = -2.0 V iii Power Up and Power Down Sequencing MRAM is protected from write operations whenever V there is a startup time before read or write operations can start. This time allows memory power ...

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Electrical Specifications Parameter Input leakage current Output leakage current Output low voltage ( mA +100 μA) OL Output high voltage ( mA -100 μA) OH Parameter AC active supply current - read modes ( mA max) OUT DD AC active supply current - write modes (V = max) DD MR4A16B (Commercial) MR4A16BC (Industrial) MR4A16BV (Extended) AC standby current (V = max ...

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TIMING SPECIFICATIONS Parameter Address input capacitance Control input capacitance Input/Output capacitance f = 1.0 MHz 3 °C, periodically sampled rather than 100% tested Parameter Logic input timing measurement reference level Logic output timing measurement reference level Logic input pulse levels Input rise/fall time Output load for low and high impedance parameters Output load for all other timing parameters Output Everspin Technologies © 2010 Table 3.1 Capacitance Symbol Table 3.2 AC Measurement Conditions Figure 3.1 Output Load Test Low and ...

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Timing Specifications Read Mode Parameter Read cycle time Address access time Enable access time 2 Output enable access time Byte enable access time Output hold from address change Enable low to output active 3 Output enable low to output active Byte enable low to output active Enable high to output Hi-Z 3 Output enable high to output Hi-Z Byte high to output Hi high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be 1 minimized or eliminated during read or write cycles. Addresses valid before or at the same time E goes low. 2 This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage (ADDRESS) Q (DATA OUT) Note: Device is continuously selected (E≤V A ...

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Timing Specifications Parameter Write cycle time 2 Address set-up time G Address valid to end of write ( G Address valid to end of write ( G Write pulse width ( high) G Write pulse width ( low) Data valid to end of write Data hold time Write low to data Hi-Z 3 Write high to output active 3 Write recovery time All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus 1 contention conditions must be minimized or eliminated during read and write cycles goes low at the same time or after W goes low, the output will remain in a high impedance state. After UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. 2 This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any given 3 voltage or temperate, t (max) < t WLQZ A (ADDRESS) E (CHIP ...

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Timing Specifications Parameter Write cycle time 2 Address set-up time Address valid to end of write (G high) Address valid to end of write (G low) Enable to end of write (G high) Enable to end of write (G low) 3 Data valid to end of write Data hold time Write recovery time All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus 1 contention conditions must be minimized or eliminated during read and write cycles goes low at the same time or after W goes low, the output will remain in a high impedance state. After UB/ LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address goes low at the same time or after W goes low, the output will remain in a high-impedance state goes high at the 3 same time or before W goes high, the output will remain in a high-impedance state. A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) UB, LB (BYTE ENABLE) D (DATA IN) ...

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Timing Specifications Table 3.6 Write Cycle Timing 3 (LB/UB Controlled) Parameter Write cycle time 2 Address set-up time Address valid to end of write (G high) Address valid to end of write (G low) Write pulse width (G high) Write pulse width (G low) Data valid to end of write Data hold time Write recovery time All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus 1 contention conditions must be minimized or eliminated during read and write cycles goes low at the same time or after W goes low, the output will remain in a high impedance state. After UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. If both byte control signals are asserted, the two signals must have no more than 2 ns skew between them. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. 2 Figure 3.6 Write Cycle Timing 3 (LB/UB Controlled) ...

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... ORDERING INFORMATION Part Number MR4A16BMA35 1 MR4A16BCMA35 MR4A16BMMA35 MR4A16BYS35 1 MR4A16BCYS35 1 MR4A16BMYS35 1 Note 1: These products are classified as Preliminary, a product in development and/or qualification that has fixed target specifications that are subject to change pending characterization results. Everspin Technologies © 2010 Figure 4.1 Part Numbering System Table 4.1 Available Parts Description 3.3 V 1Mx16 MRAM 48-BGA 3.3 V 1Mx16 MRAM 48-BGA 1 1Mx16 1 3.3 V MRAM 48-BGA 3.3 V 1Mx16 MRAM 54-TSOP 3.3 V 1Mx16 MRAM 54-TSOP ...

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MECHANICAL DRAWING BOTTOM VIEW (DATUM (DATUM A) SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ref Min Nominal A 1.19 A1 0.22 b 0.31 D 10.00 BSC E 10.00 BSC ...

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MECHANICAL DRAWING 0.71 REF. C SEATING PLANE Ref Min Nominal A A1 0.05 A2 0.95 b 0.30 c 0.12 D 22.10 E 11.56 E1 10.03 e 0.80 BSC L 0.40 L1 0.80 REF R1 0.12 R2 0.12 θ ...

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REVISION HISTORY Revision Date 1 May 29, 2009 2 July 27, 2009 3 Nov 26, 2009 4 Mar 10, 2010 5 Apr 7, 2010 How to Reach Us: Home Page: www.everspin.com E-Mail: support@everspin.com orders@everspin.com sales@everspin.com USA Everspin Technologies 1300 N. Alma School Road, CH-409 Chandler, Arizona 85224 +1-877-347-MRAM (6726) +1-480-347-1111 Europe, Middle East and Africa support.europe@everspin.com Workingham, ...