M395T5750EZ4CE65 Samsung Semiconductor, M395T5750EZ4CE65 Datasheet - Page 26

• Manufacturer Part Number: M395T5750EZ4CE65
• Manufacturer: Samsung Semiconductor

Specifications of M395T5750EZ4CE65

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240FBDIMM
• Device Core Size: 72b
• Organization: 256Mx72
• Total Density: 2GByte
• Chip Density: 512Mb
• Package Type: FBDIMM
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Number Of Elements: 36
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / RoHS Status: Compliant

11. The received differential signal must satisfy both this ratio as well as the absolute maximum AC peaktopeak common mode specification. For example,
12. One of the components that contribute to the deterioration of the return loss is the ESD structure which needs to be carefully designed.
13. The termination small signal resistance; tolerance across voltage from 100 mV to 400 mV shall not exceed +/-5 W with regard to the average of the
14. This number represents the lane-to-lane skew between TX and RX pins and does not include the transmitter output skew from the component of the
15. Measured from the reference clock edge to the center of the input eye. This specification must be met across specified voltage and temperature ranges
16. This bandwidth number assume the specified minimum data transition density. Maximum jitter at 0.2 MHz is 0.05 UI,
17. The specified time includes the time required to forward the El entry condition.
18. BER per differential lane.
V
(V
V
R
FBDIMM
RX-DIFFp-p
RX-CM-AC
RX-MATCH-DC
RX-CM
if VRX-DIFFp-p is 200 mV, the maximum AC peak-to peak common mode is the lesser of (200 mV*0.45=90 mV)and VRX-CM-AC-p-p.
values measured at 100 mV and at 400 mV for that pin.
end-to-end channel skew in the AMB specification.
for a single component. Drift rate of change is significantly below the tracking capability of the receiver.
= DC(avg) of [V
=((Max[V
= 2x[V
= 2x((R
RX-D
RX-D+
RX-D+
+-V
RX-D+
+ V
RX-D-
-R
RX-D
+ V
RX-D-
] (EQ5)
RX-D-
)/2)((Min [V
)/(R
] /2) (EQ 6)
RX-D+
RX-D+
+ R
RX-D-
+ V
) (EQ 8)
RX-D-
)/2) (EQ 7)
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Rev. 1.51 January 2008
DDR2 SDRAM