MPC2605ZP66 Freescale, MPC2605ZP66 Datasheet - Page 25

• Manufacturer Part Number: MPC2605ZP66
• Manufacturer: Freescale

Specifications of MPC2605ZP66

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

DH0 – DH31,
READ/WRITE SNOOP HIT (DIRTY L2 AND
PROCESSOR LINE)
L2 cache line is shown in Figure 8. The processor has
a dirty copy of the cache line. In this case, both the
processor and MPC2605 assert ARTRY. This situation
is detected by sampling CPU BR in the BR window, as
MOTOROLA
DL0 – DL31
CPU DBG
L2 CLAIM
A0 – A31
CPU BG
CPU BR
An illustration of a read or write snoop hit to a dirty
L2 DBG
ARTRY
L2 BR
L2 BG
AACK
DBB
CLK
TS
TA
LEGEND
Signal driven to the MPC2605
Signal driven by the MPC2605
High-Z
Figure 8. Read or Write Snoop Hit to Dirty L2 Cache Line and Dirty Processor Cache Line
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Integrated Secondary Cache for Microprocessors
Freescale Semiconductor, Inc.
A
For More Information On This Product,
2
That Implement PowerPC Architecture
3
Go to: www.freescale.com
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described in the previous example. If CPU BR is
asserted in the BR window, the MPC2605 will negate
L2 BR. It will also ignore assertions of L2 BG. This
allows the processor to write back its dirty cache line.
At this time, the MPC2605 will either update or
invalidate its copy depending on whether it is a snoop
read or snoop write.
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7
A
8
A1
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10
A2
11
A3
A
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A4
MPC2605/D
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14
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