MPC2605ZP66 Freescale, MPC2605ZP66 Datasheet - Page 29

• Manufacturer Part Number: MPC2605ZP66
• Manufacturer: Freescale

Specifications of MPC2605ZP66

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

BYPASS TAP INSTRUCTION
loaded at power up. This instruction will place a single
shift register between TDI and TDO during the
SHIFT-DR state of the TAP controller. This allows the
board level scan path to be shortened to facilitate
testing of other devices in the scan path.
MOTOROLA
The BYPASS instruction is the default instruction
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising
1
0
TEST-LOGIC
RUN-TEST/
0
RESET
edge of TCK.
IDLE
1
Integrated Secondary Cache for Microprocessors
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 11. TAP Controller State Diagram
That Implement PowerPC Architecture
Go to: www.freescale.com
1
0
1
CAPTURE-DR
UPDATE-DR
DR-SCAN
EXIT1-DR
PAUSE-DR
EXIT2-DR
SHIFT-DR
SELECT
0
0
1
0
1
1
0
DISABLING THE TEST ACCESS PORT AND
BOUNDARY SCAN
four pins used for the test access port. To circuit
disable the device, TCK must be tied to V
preclude mid-level inputs. TRST should be tied to V
to ensure proper HRESET operation. Although TDI
and TMS are designed in such a way that an undriven
input will produce a response equivalent to the
application of a logic 1, it is still advisable to tie these
inputs to V
remain unconnected.
It is possible to use this device without utilizing the
0
0
1
1
DD
through a 1K resistor. TDO should
1
0
1
CAPTURE-IR
UPDATE-IR
IR-SCAN
EXIT1-IR
PAUSE-IR
EXIT2-IR
SELECT
SHIFT-IR
0
0
1
0
1
1
0
0
0
1
1
SS
MPC2605/D
to
SS
29