MCM69C433TQ15 Freescale, MCM69C433TQ15 Datasheet - Page 8

• Manufacturer Part Number: MCM69C433TQ15
• Manufacturer: Freescale

Specifications of MCM69C433TQ15

• Operating Temperature (max): 85C
• Package Type: TQFP
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

MCM69C433 SCM69C433
8
INTERRUPT BIT DEFINITIONS
INSERT VALUE
into the CAM. The contents of I/O registers 0 – 3 are con-
catenated, with bit 15 of register 3 as the most significant bit,
and bit 0 of register 0 as the least significant bit.
the resulting 64–bit value is written to the first available loca-
tion in the entry queue, and is immediately available for
matching. If a buffered insert–value instruction is attempted
when the entry queue is full (indicated by bit 5 of the flag reg-
ister = 1), no value is written, an error code of FFF8 16 is re-
turned in the error code register, and the error–condition flag
(bit 7) is set in the flag register. An interrupt is generated, if
enabled by bit 0 of the interrupt register being set.
concatenated 64–bit value is written directly to the CAM
array. If an insert–value instruction is attempted when in
fast–entry mode and the table is full, no value is written, an
error code of FFF9 16 is returned in the error code register,
This instruction is used to load a new match/output value
If the MCM69C433 is running in the buffered–entry mode,
If the MCM69C433 is running in the fast–entry mode, the
Bit 0: 1 = Enable interrupt on insert with full entry
Bit 1: 1 = Enable interrupt on insert with full table
Bit 2: 1 = Enable interrupt on completion of
Bit 3: 1 = Enable interrupt on completion of
Bit 4: 1 = Enable interrupt on failed attempt to enter
Bit 5: 1 = Enable interrupt on CAM table reaching
Bit 6: 1 = Enable interrupt on fast read with non–empty
Bit 7: 1 = Enable interrupt on illegal instruction
INSERT VALUE
DELETE VALUE
CHECK FOR VALUE
INITIALIZE TABLE
FAST–ENTRY MODE
BUFFERED–ENTRY MODE
SET ATM MODE
RETURN ENTRY COUNT
SET GLOBAL–MASK REGISTER
SET ALMOST–FULL POINT
SET FAST–READ REGISTER
FAST READ
queue
CHECK–FOR–VALUE instruction
INITIALIZE–TABLE instruction
fast–entry mode
almost–full point
queue
Operation
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 1. MCM69C433 Operation Summary
Loads a new entry into the CAM table
Removes an entry from the CAM table
Runs a match cycle via the control port
Prepares CAM table for matching
Selects entry mode suited for initial CAM table load
Selects entry mode suited for simultaneous loading
and matching
Enter mode that provides concurrent VPC/VCC
search
Determines number of entries in CAM
Determines match bits to be checked in a match
operation
Defines CAM almost–full condition
Defines table entry that is output by the fast–read
operation
Outputs one CAM table entry
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Description
INSTRUCTION SET DETAILS
writing data and instructions via the control port. In the gen-
eral case, required data is loaded into I/O registers 0 – 3,
then an instruction is issued by writing an operation code to
the operation register. As a result of running an instruction,
the CAM table can be modified, bit(s) can be set in the flag
register, error codes can be returned in the error code regis-
ter, and an interrupt can be generated if enabled. For a par-
ticular condition to generate an interrupt, the interrupt
register bit specific to that condition must be set. The user
should verify that the last operation complete bit (bit 10) of
the flag register is set before executing the next instruction, if
the instruction just executed modifies I/O registers. See the
Simultaneous Port Operations section for any exceptions.
and the error–condition flag (bit 7) is set in the flag register.
(The table–full condition is indicated by bit 6 of the flag regis-
ter being set.) An interrupt is generated, if enabled by bit 1 of
the interrupt register being set.
entry is made in the table that duplicates an existing match
pattern, it will overwrite the entry already in the CAM table, if
the CAM is in buffered–entry mode. The user must ensure
that no entries with the same match pattern are inserted in
fast–entry mode.
DELETE VALUE
from the CAM. The contents of I/O registers 0 – 3 are con-
catenated, with bit 15 of register 3 as the most significant bit,
and bit 0 of register 0 as the least significant bit. The bits that
have a 0 in the corresponding bit of the global–mask register
are used to find a matching entry in the CAM table. If such an
entry is found, it is invalidated. Note that any bit that is not a
The MCM69C433 is prepared for match operations by
Only one entry is allowed for a given match pattern. If an
This instruction is used to remove a match/output value
OP Code (Base 16)
MOTOROLA FAST SRAM
0001 or 000E
0002 or 000D
0000 or 000F
000B
000A
0006
0004
0005
0008
0003
0007
0009