MCM69C433TQ15 Freescale, MCM69C433TQ15 Datasheet - Page 3

• Manufacturer Part Number: MCM69C433TQ15
• Manufacturer: Freescale

Specifications of MCM69C433TQ15

• Operating Temperature (max): 85C
• Package Type: TQFP
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

MOTOROLA FAST SRAM
NOTE: Assert KMODE 1 clock cycle after RESET is deasserted.
PIN DESCRIPTIONS
41, 48, 54, 59, 65, 71,
4, 10, 16, 22, 27, 33,
3, 9, 15, 21, 28, 34,
1, 2, 5 – 8, 11 – 14
40, 53, 60, 66, 72,
17 – 20, 23 – 26,
67 – 70, 73 – 76,
79 – 82, 85 – 88,
93 – 96, 99, 100,
29 – 32, 35 – 38
Pin Locations
77, 84, 91, 97
78, 83, 90, 98
42 – 44
58
61
57
39
47
89
92
64
62
56
46
52
50
55
51
49
63
45
KMODE
RESET
K
MQ31 – MQ0
DQ15 – DQ0
Symbol
A2 – A0
KMODE
DTACK
RESET
LH/SM
TRST
TCK
TDO
TMS
VPC
V DD
V SS
SEL
IRQ
MC
TDI
WE
MS
LL
G
K
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Output
Output
Output
Output
Output
Output
Supply
Supply
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
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3–bit control port address bus.
Control port data transfer acknowledge (Open Drain).
16–bit bidirectional control port data bus.
Output Enable control of MQ31 – MQ0.
Control port interrupt (Open Drain).
Interface Clock, max frequency of 66 MHz.
See Note.
Latch High/Start Match. Initiates match sequence on match data present on
MQ31 – MQ0.
Latch Low. Latches low order bits if match width is > 32 bits.
Match Complete (Open Drain).
32–bit common I/O CAM data. Used for input of match RAM and data RAM
values.
Match Successful (Open Drain).
Resets chip to a known state.
Control port chip select, active low.
Test Clock, part of JTAG interface.
Test Data In, part of JTAG interface.
Test Data Out, part of JTAG interface.
Test Mode Select, part of JTAG interface.
Tap Reset part of JTAG interface.
Virtual Path Circuit. Used in ATM mode to indicate a virtual path circuit match has
occurred (Open Drain).
Control port Write Enable.
Power Supply: 3.3 V 5%.
Ground.
Description
MCM69C433 SCM69C433
3