MCM69C433TQ15 Freescale, MCM69C433TQ15 Datasheet - Page 10

• Manufacturer Part Number: MCM69C433TQ15
• Manufacturer: Freescale

Specifications of MCM69C433TQ15

• Operating Temperature (max): 85C
• Package Type: TQFP
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

MCM69C433 SCM69C433
10
SET FAST–READ REGISTER VALUE
the fast–read operation. The least significant 14 bits of I/O
register 0 are copied to the fast–read register. The queue
must be empty when this instruction is executed.
FAST READ
in the CAM table. The fast–read register is used to specify
the appropriate entry, and is then auto–incremented. As a re-
sult, successive execution of multiple fast–read operations
will provide access to contiguous entries in the CAM table.
of register 3 as the most significant bit, and bit 0 of register 0
as the least significant bit.
entry queue is empty, as reflected by the queue–empty flag
being set (bit 4 of the flag register.) If this operation is at-
tempted while the entry queue is not empty, the value
FFFC 16 is written to the error code register, the error–condi-
tion flag (bit 7) is set in the flag register, and an interrupt is
generated if enabled by bit 7 of the interrupt register.
SET ATM MODE
simultaneous searching for virtual path circuits (VPCs) and
virtual connection circuits (VCCs). A VCC is detected when
both the virtual path identifier (VPI) and the virtual circuit
identifier (VCI) of an incoming cell match an entry in the
CAM. A VPC match occurs when the VPI of an incoming cell
matches the VPI field of a CAM entry that has all 1s as its
VCI. A VPC match is signalled by the assertion of the VPC
pin along with the MS pin. At 66 MHz, a match is completed
in 240 ns, whether the applied VPI/VCI belongs to a VCC or
a VPC.
each entry. The VPI match data must occupy bits 48 – 59.
The VPI can be limited to bits 48 – 55, if the switch handles
only User–Network Interface (UNI) protocols. The mask reg-
ister should be used to “don’t care” any unused bits beyond
the VPI field. Entering ATM mode will set bit 9 of the flag reg-
ister.
written (right justified) to I/O register 3, FFFF 16 is written to
I/O register 2 as the VCI field, the upper half of the desired
output word is written to I/O register 1, and the lower half of
the desired output word is written to I/O register 0. Then, the
“INSERT VALUE” instruction is written to the operation regis-
ter.
placed in bits 0 – 15 of the MQ port. The VPI is expected on
bits 16 – 27, or bits 16 – 23 in the UNI case.
in the following way when the MCM69C433 is in ATM mode.
If you try to add a VCC with the same VPI as an existing
VPC, you overwrite the VPC. If you try to delete a VCC when
the VCC is not in the table, but a VPC with that VPI is in the
table, the VPC will be deleted.
VCC entry and VPC entry with matching VPIs. Violation of
this requirement may lead to unpredictable behavior.
This operation defines the table address that is output by
This operation is used to output the contents of one entry
The CAM entry is copied to I/O registers 0 – 3, with bit 15
The fast–read instruction can only be executed while the
When the MCM69C433 is placed in ATM mode, it provides
The VCI match field must be defined as bits 32 – 47 of
To load a VPC into the CAM table, the desired VPI value is
When performing a match operation, the VCI must be
Buffered–entry mode insertions and deletions are modified
The CAM table should never contain, simultaneously, a
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application requires extra bits. The use of bits 0 – 31 for
matching is not supported in ATM mode.
or 16 clock cycles, after assertion of the SM signal. How-
ever, if entries need to be added to or deleted from the CAM,
idle time is needed between match output and match
requests for control port insertions and deletions. At 66 MHz,
the match duty cycle should be defined at least at 20 clock
cycles (300 ns), leaving 2 clock cycles for insertions/
deletions. The additional clock cycles are used for holding
the match data on the MQ bus. Therefore, every 20 clock
cycles, when a match operation and data output are com-
pleted, SM can be asserted.
the highest value at the bottom. If an entry with a match data
value smaller than any other entry is continually added or
dropped from the table, worst–case scenario occurs causing
shifting of all other entries. The idle time, in terms of the num-
ber cycles, needed to perform a worst–case insertion and/or
deletion is given by the formula 32,768 x MDC / (MDC – 18)
cycles, where MDC is the match duty cycles. For example, if
match requests are occurring every 20 clock cycles:
end of the table and deletions occurring at the other end, or
when insertions and/or deletions take place toward the
middle of the table. The latter scenario would consist of
approximately half the total entries being shifted. The idle
time, in terms of the number of cycles, needed to perform a
typical insertion and/or deletion is given by the formula
16,384 x MDC / (MDC – 18) cycles, where MDC is the match
duty cycles. For example, if match requests are occurring
every 20 clock cycles:
depicted in Figure 3. In general, the time for an insertion or
deletion is proportional to its distance from the end of the
CAM table. That is, entries with the largest match value take
the least time to insert or delete, while entries with the small-
est values take the most time. Therefore, the effective rate of
Bits 60 – 63 may be used for matching in ATM mode if the
At 66 MHz, the MCM69C433 completes a match 240 ns,
Entries are stored from least value at the top of the table to
At 66 MHz (15 ns per cycle)
If both insertions and deletions are occurring
More typical cases consist of insertions occurring at one
At 66 MHz (15 ns per cycle)
If both insertions and deletions are occurring
The number of insertion/deletion pairs for both cases are
= 203 insertion/deletion pairs per sec (typical case).
= 102 insertion/deletion pairs per sec (worst–case).
32,768 x 20 clock cycles
16,384 x 20 clock cycles
20 clock cycles – 18
20 clock cycles – 18
= 0.0049152 sec per insert or deletion.
= 0.0024576 sec per insert or deletion.
MATCH DUTY CYCLE
= 327,680 clock cycles
= 163,840 clock cycles
MOTOROLA FAST SRAM