NP5Q128A13ESFC0E Micron Technology Inc, NP5Q128A13ESFC0E Datasheet - Page 44

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NP5Q128A13ESFC0E

Manufacturer Part Number
NP5Q128A13ESFC0E
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of NP5Q128A13ESFC0E

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Figure 20. Power-up timing
Table 9.
1. These parameters are characterized only.
Initial delivery state
The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte
contains FFh). The status register contains 00h (all status register bits are 0).
V CC (max)
V CC (min)
Symbol
t
t
PUW
V
VSL
WI
V WI
(1)
(1)
(1)
V CC
V
Time delay to write instruction
Write inhibit voltage
Power-up timing and V
Reset state
CC
device
of the
(min) to S Low
Program, erase and write commands are rejected by the device
Chip selection not allowed
Parameter
WI
threshold
tPUW
tVSL
Read access allowed
Min
100
1.5
1
Device fully
accessible
Max
2.5
10
AI04009C
Unit
time
ms
µs
V

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