NP5Q128A13ESFC0E Micron Technology Inc, NP5Q128A13ESFC0E Datasheet - Page 16

• Manufacturer Part Number: NP5Q128A13ESFC0E
• Manufacturer: Micron Technology Inc

Specifications of NP5Q128A13ESFC0E

• Lead Free Status / RoHS Status: Supplier Unconfirmed

4.8
4.8.1
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Protection modes
There are protocol-related and specific hardware and software protection modes. They are
described below.
Protocol-related protections
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
Omneo™ P5Q PCM features the following data protection mechanisms:
n
n
n
n
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Power on reset and an internal timer (t
changes while the power supply is outside the operating specification
Program, erase, and write status register are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution
All instructions that modify data must be preceded by a write enable (WREN) instruction
to set the write enable latch (WEL) bit. This bit is returned to its reset state by the following
events:
– Power-up
– Write disable (WRDI) instruction completion
– Write status register (WRSR) instruction completion
– Page program (PP) instruction completion
– Dual input fast program (DIFP) instruction completion
– Quad input fast program (QIFP) instruction completion
– Sector erase (SE) instruction completion
– Bulk erase (BE) instruction completion
The Block Protect bits (see
(see
only. This is the Software Protect Mode (SPM).
The Write Protect (W) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits,
Top/Bottom (TB) bit and Status Register Write Disable (SRWD) bit to be protected. This
is the Hardware Protected Mode (HPM). For more details, see
register
Section 6.4.4: Top/bottom
(WRSR).
Section 6.4.3: BP3, BP2, BP1, BP0
bit) allow part of the memory to be configured as read-
PUW
) can provide protection against inadvertent
Section 6.5: Write status
bits) and top/bottom bit