MT45W8MW16BGX-701 IT Micron Technology Inc, MT45W8MW16BGX-701 IT Datasheet
MT45W8MW16BGX-701 IT
Specifications of MT45W8MW16BGX-701 IT
Related parts for MT45W8MW16BGX-701 IT
MT45W8MW16BGX-701 IT Summary of contents
Page 1
... Operating temperature range – Wireless (–30°C to +85°C) – Industrial (–40°C to +85°C) GX Notes: 1. The 3.6V I/O and the 133MHz clock fre- –70 –85 MT45W8MW16BGX-7013LWT Micron Technology, Inc., reserves the right to change products or specifications without notice 1.5 54-Ball VFBGA Ball Assignment 1 ...
Page 2
Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
List of Figures Figure 1: 54-Ball VFBGA Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
List of Tables Table 1: VFBGA Ball Descriptions ...
Page 5
... General Description Micron developed for low-power, portable applications. The MT45W8MW16BGX device has a 128Mb DRAM core, organized as 8 Meg x 16 bits. These devices include an industry- standard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-power SRAM or pseudo-SRAM offerings. ...
Page 6
Figure 2: Functional Block Diagram – 8 Meg x 16 A[22:0] CE# WE# OE# CLK Control ADV# Logic CRE WAIT LB# UB# Notes: 1. Functional block diagrams illustrate simplified device operation. See ball descriptions (Table 1 on page 7), bus ...
Page 7
Table 1: VFBGA Ball Descriptions Note 1 VFBGA Assignment Symbol J4, E3, H6, G2, H1, A[22:0] D3, E4, F4, F3, G4, G3, H5, H4, H3, H2, D4, C4, C3, B4, B3, A5, A4 CLK J3 ADV# A6 CRE ...
Page 8
Table 2: Bus Operations Asynchronous Mode BCR[15 Power Active Read Write Active Standby Standby No operation Idle Active Configuration register write Active Configuration register read DPD Deep power-down Burst Mode BCR[15 Power Async read Active Async ...
Page 9
Part-Numbering Information Micron CellularRAM devices are available in several different configurations and densities. (See Figure 3.) Figure 3: Part Number Chart Micron Technology Product Family 45 = PSRAM/CellularRAM memory Operating Core Voltage W = 1.70–1.95V Address Locations M = Megabits ...
Page 10
... Functional Description In general, the MT45W8MW16BGX device is a high-density alternative to SRAM and pseudo-SRAM products, popular in low-power, portable applications. The MT45W8MW16BGX contains a 134,217,728-bit DRAM core, organized as 8,388,608 addresses by 16 bits. The device implements the same high-speed bus interface found on burst mode Flash products. ...
Page 11
Figure 5: READ Operation (ADV# LOW) CE# OE# WE# ADDRESS DATA LB#/UB# Notes: 1. ADV# must remain LOW for page mode operation. Figure 6: WRITE Operation (ADV# LOW) CE# OE# WE# ADDRESS DATA LB#/UB# PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. ...
Page 12
Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the low- order address. ...
Page 13
Burst Mode Operation Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a multi-clock sequence that must be performed in an ordered fashion. After CE# goes LOW, the address to access is latched on the ...
Page 14
Figure 8: Burst Mode READ (4-word burst) CLK A[22:0] ADV# CE# OE# WE# WAIT DQ[15:0] LB#/UB# Notes: 1. Non-default BCR settings for burst mode READ (4-word burst): Fixed or variable latency; latency code two (three clocks); WAIT active LOW; WAIT ...
Page 15
Mixed-Mode Operation The device supports a combination of synchronous READ and asynchronous READ and WRITE operations when the BCR is configured for synchronous operation. The asyn- chronous READ and WRITE operations require that the clock (CLK) remain LOW during the ...
Page 16
LB#/UB# Operation The LB# enable and UB# enable signals support byte-wide data WRITEs. During WRITE operations, any disabled bytes will not be transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the ...
Page 17
Low-Power Operation Standby Mode During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion of ...
Page 18
Access Using CRE The registers can be accessed using either a synchronous or an asynchronous operation when the control register enable (CRE) input is HIGH. (See Figures 12 through 15 on pages 18 through 21.) When CRE is LOW, a ...
Page 19
Figure 13: Configuration Register WRITE, Synchronous Mode Followed by READ ARRAY Operation CLK Latch Control Register Value A[22:0] OPCODE (except A[19:18 A[19:18 CRE t SP ADV CSP CE# OE WE# ...
Page 20
Figure 14: Register READ, Asynchronous Mode Followed by READ ARRAY Operation A[22:0] (except A[19:18]) Select Register 1 A[19:18] CRE ADV# CE# OE# WE# LB#/UB# DQ[15:0] Notes: 1. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to ...
Page 21
Figure 15: Register READ, Synchronous Mode Followed by READ ARRAY Operation CLK Latch Control Register Value A[22:0] (except A[19:18 A[19:18 CRE t SP ADV CSP CE# OE# WE LB#/UB# t ...
Page 22
Software Access Software access of the registers uses a sequence of asynchronous READ and asynchro- nous WRITE operations. The contents of the configuration registers can be modified and all registers can be read using the software sequence. The configuration registers ...
Page 23
Figure 17: Read Configuration Register ADDRESS CE# OE# WE# LB#/UB# DATA Notes possible that the data stored at the highest memory location will be altered if the data at the falling edge of WE# is not 0000h, ...
Page 24
Bus Configuration Register (BCR) The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Figure 18 describes the control bits in the BCR. At power-up, ...
Page 25
Burst Length (BCR[2:0]) Default = Continuous Burst Burst lengths define the number of words the device outputs during burst READ and WRITE operations. The device supports a burst length 16 words. The device can also ...
Page 26
Sequence and Burst Length Table 3: 4-Word Burst Starting Burst Wrap Address Length BCR [3] Wrap (Decimal) Linear 0 0-1-2-3 1 1-2-3-4 2 2-3-4-5 3 3-4-5 ... 14 15 ... 30 31 Drive Strength ...
Page 27
WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. ...
Page 28
Figure 21: WAIT Configuration During Burst Operation CLK WAIT WAIT DQ[15:0] Notes: 1. Non-default BCR setting: WAIT active LOW. Latency Counter (BCR[13:11]) Default = Three Clock Latency The latency counter bits determine how many clocks occur between the beginning of ...
Page 29
Figure 22: Latency Counter (Variable Initial Latency, No Refresh Collision CLK A[22:0] Valid Address ADV DQ[15: DQ[15: Table 6: Fixed ...
Page 30
Figure 23: Latency Counter (Fixed Latency CLK A[22:0] Valid Address ADV CE DQ[15: (READ DQ[15: (WRITE) ...
Page 31
Refresh Configuration Register (RCR) The RCR defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Figure 24 describes ...
Page 32
Table 7: 128Mb Address Patterns for PAR (RCR[ RCR[2] RCR[1] RCR[ DPD (RCR[4]) Default ...
Page 33
Electrical Specifications Table 9: Absolute Maximum Ratings Parameter Voltage to any ball except Voltage on V supply relative Voltage supply relative Storage temperature (plastic) Operating temperature ...
Page 34
Table 10: Electrical Characteristics and Operating Conditions Wireless temperature (–30ºC < T Description Conditions Supply voltage I/O supply voltage Input high voltage Input low voltage Output high voltage I = –0.2mA OH Output low voltage I = +0.2mA OL V ...
Page 35
Table 11: PAR Specifications and Conditions Description V Partial-array refresh standby IN current Notes PAR must be driven to either V power-up or when entering standby mode. Figure 25: Typical Refresh Current vs. Temperature (I 140 130 120 ...
Page 36
Table 12: Deep Power-Down Specifications Typical (TYP) I value applies across all operating temperatures and voltages ZZ Description Deep Power-Down Table 13: Capacitance These parameters are verified in device characterization and are not 100-percent tested Description Input Capacitance Input/Output Capacitance ...
Page 37
Timing Requirements Table 14: Asynchronous READ Cycle Timing Requirements All tests performed with outputs configured for default setting of one-half drive strength, (BCR[5:4] = 01b) Parameter Address access time ADV# access time Page access time Address hold from ADV# HIGH ...
Page 38
Table 15: Burst READ Cycle Timing Requirements All tests performed with outputs configured for default setting of one-half drive strength (BCR[5:4] = 01b). Parameter Address access time (fixed latency) ADV# access time (fixed latency) Burst to READ access time (variable ...
Page 39
Table 16: Asynchronous WRITE Cycle Timing Requirements Parameter Address and ADV# LOW setup time Address HOLD from ADV# going HIGH Address setup to ADV# going HIGH Address valid to end of WRITE LB#/UB# select to end of WRITE CE# LOW ...
Page 40
Table 17: . Burst WRITE Cycle Timing Requirements Parameter Address and ADV# LOW setup time Address hold from ADV# HIGH (fixed latency) CE# HIGH between subsequent burst or mixed-mode operations Maximum CE# pulse width CE# LOW to WAIT valid Clock ...
Page 41
Timing Diagrams Figure 28: Initialization Period Figure 29: DPD Entry and Exit Timing Parameters CE# Write DPD enabled RCR[ Table 18: Initialization and DPD Timing Parameters Parameter Time from DPD entry to DPD ...
Page 42
Figure 30: Asynchronous READ A[22:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory Valid Address ...
Page 43
Figure 31: Asynchronous READ Using ADV# A[22:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory V IH Valid Address ...
Page 44
Figure 32: Page Mode READ A[22:4] A[3:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async/ Page/Burst CellularRAM 1.5 Memory ...
Page 45
Figure 33: Single-Access Burst READ Operation – Variable Latency CLK A[22:0] ADV# CE# OE# WE# LB#/UB# WAIT DQ[15:0] Notes: 1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - ...
Page 46
Figure 34: 4-Word Burst READ Operation – Variable Latency V IH CLK Valid A[22:0] Address ADV CSP V IH CE# V ...
Page 47
Figure 35: Single-Access Burst READ Operation – Fixed Latency V IH CLK A[22:0] Valid Address ADV CSP OE# ...
Page 48
Figure 36: 4-Word Burst READ Operation – Fixed Latency V IH CLK Valid A[22:0] Address AVH ADV CSP V IH CE# V ...
Page 49
Figure 37: READ Burst Suspend V IH CLK Valid A[22:0] Address ADV CSP OE# ...
Page 50
Figure 38: Burst READ at End of Row (Wrap Off CLK CLK V IH A[22: ADV LB#/UB CE OE# ...
Page 51
Figure 39: CE#-Controlled Asynchronous WRITE A[22:0] ADV# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async Valid Address V IL ...
Page 52
Figure 40: LB#/UB#-Controlled Asynchronous WRITE A[22:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async Valid Address V ...
Page 53
Figure 41: WE#-Controlled Asynchronous WRITE A[22:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async Valid Address ...
Page 54
Figure 42: Asynchronous WRITE Using ADV# A[22:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef80ec6f79/Source: 09005aef80ec6f65 128mb_burst_cr1_5_p26z__2.fm - Rev. H 9/07 EN 128Mb: 8 Meg x 16 Async/Page/Burst CellularRAM 1.5 Async Valid Address V IL ...
Page 55
Figure 43: Burst WRITE Operation – Variable Latency Mode V IH CLK A[22:0] Valid Address ADV ...
Page 56
Figure 44: Burst WRITE Operation – Fixed Latency Mode V IH CLK A[22:0] Valid Address ADV ...
Page 57
Figure 45: Burst WRITE at End of Row (Wrap Off CLK CLK V IH A[22: ADV LB#/UB CE WE# ...
Page 58
Figure 46: Burst WRITE Followed by Burst READ t CLK V IH CLK A[22:0] Valid Address ADV LB#/UB ...
Page 59
Figure 47: Burst READ Interrupted by Burst READ or WRITE V IH CLK Valid A[22:0] Address ADV CSP V IH CE# ...
Page 60
Figure 48: Burst WRITE Interrupted by Burst WRITE or READ – Variable Latency Mode V IH CLK A[22:0] Valid V Address ADV ...
Page 61
Figure 49: Burst WRITE Interrupted by Burst WRITE or READ – Fixed Latency Mode V IH CLK A[22:0] Valid V Address IL t AVH ADV ...
Page 62
Figure 50: Asynchronous WRITE Followed by Burst READ V IH CLK A[22:0] Valid Address Valid Address AVS t AVH ADV ...
Page 63
Figure 51: Asynchronous WRITE (ADV# LOW) Followed by Burst READ VIH CLK VIL t WC VIH A[22:0] Valid Address Valid Address VIL t AW VIH ADV# VIL t BW VIH LB#/UB# VIL t CW VIH CE# VIL VIH OE# t ...
Page 64
Figure 52: Burst READ Followed by Asynchronous WRITE (WE#-Controlled CLK A[22:0] Valid Address ADV CSP V IH CE# V ...
Page 65
Figure 53: Burst READ Followed by Asynchronous WRITE Using ADV CLK A[22:0] Valid Address ADV CSP V IH CE# ...
Page 66
Figure 54: Asynchronous WRITE Followed by Asynchronous READ – ADV# LOW V IH A[22:0] Valid Address ADV LB#/ ...
Page 67
Figure 55: Asynchronous WRITE Followed by Asynchronous READ V IH A[22:0] Valid Address AVS ADV CVS V IH LB#/UB CE ...
Page 68
... All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. The MT45W8MW16BGX uses “green” packaging. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron Technology, Inc ...