SLATA5GM1U STEC, SLATA5GM1U Datasheet - Page 18

• Manufacturer Part Number: SLATA5GM1U
• Manufacturer: STEC

Specifications of SLATA5GM1U

• Lead Free Status / RoHS Status: Compliant

SLATAxxx(M/G)M1U(I)
Datasheet
3.3.7 True IDE Mode Register Access
Cycle time (min)
Address valid to
-IORD/-IOWR
(min) setup
-IORD/-IOWR
pulse width 8bit
(min)
-IORD/-IOWR
recovery time
(min)
-IOWR data
setup (min)
-IOWR data hold
(min)
-IORD data
setup (min)
-IORD data hold
(min)
-IORD data
tristate (max)
Addresses valid
to -IOCS16
assert. (max)
Address valid to
-IOCS16 release
(max)
-IORD/-IOWR to
address valid
hold
Parameter
Symbol
Table 17: True IDE Mode Register Access AC Characteristics
t6z
t2i
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
Mode0
600
290
30
60
70
—
60
30
50
90
20
5
Mode1
61000-04497-104, January 2007
383
290
50
45
20
35
30
50
45
15
—
5
Mode2
330
290
30
30
15
20
30
40
30
10
—
5
Mode3
180
N/A
N/A
30
80
70
30
10
20
30
10
5
Mode4
120
N/A
N/A
25
70
25
20
10
20
30
10
5
Mode5
100
N/A
N/A
15
65
25
20
15
20
10
5
5
ATA PC Card
Mode6
N/A
N/A
80
10
55
20
15
10
20
10
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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