SLATA5GM1U STEC, SLATA5GM1U Datasheet - Page 13
![no-image](/images/no-image-200.jpg)
SLATA5GM1U
Manufacturer Part Number
SLATA5GM1U
Description
Manufacturer
STEC
Datasheet
1.SLATA5GM1U.pdf
(32 pages)
Specifications of SLATA5GM1U
Lead Free Status / RoHS Status
Compliant
SLATAxxx(M/G)M1U(I)
Datasheet
3.3.2 PC Card Memory Mode Attribute Memory Write
Write Cycle Time
Write Pulse Width
Address Setup Time
Address Setup Time (-WE)
-CE Setup Time (-WE)
Data Setup Time (-WE)
Data Hold Time
Write Recovery Time
Output Disable Time (-WE)
Output Disable Time (-OE)
Output Enable Time (-WE)
Output Enable Time (-OE)
Output Enable Setup Time (-WE)
Output Enable Hold Time (-WE)
-CE Setup Time
-CE Hold Time
Parameter
Table 12: PC Card Memory Mode Attribute Memory Write AC Characteristics
Figure 3: PC Card Memory Mode Attribute Memory Write Timing Diagram
61000-04497-104, January 2007
tsu(CE-WEH)
tsu(D-WEH)
tsu(A-WEH)
tsu(OE-WE)
th(OE-WE)
trec(WE)
tdis(WE)
tdis(OE)
ten(WE)
Symbol
ten(OE)
tsu(CE)
tw(WE)
th(CE)
tsu(A)
tc(W)
th(D)
IEEE Symbol
tWLWH
tWMDX
tDVWH
tWMAX
tAVWL
tAVAV
—
—
—
—
—
—
—
—
—
—
Min (ns)
250
150
180
180
30
80
30
30
10
10
20
5
5
0
ATA PC Card
Max (ns)
100
100
13