HB28K032MM3 Renesas Electronics America, HB28K032MM3 Datasheet - Page 3

• Manufacturer Part Number: HB28K032MM3
• Manufacturer: Renesas Electronics America
• Type: MultiMedia Cardr

Specifications of HB28K032MM3

• Density: 32MByte
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (min): -25C
• Operating Temperature (max): 85C
• Package Type: Not Required
• Mounting: Surface Mount
• Pin Count: 7
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Programmable: Yes
• Lead Free Status / RoHS Status: Compliant

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3
Block Diagram
All units in these Renesas MultiMediaCards are clocked by an internal clock generator. The Interface
driver unit synchronizes the DAT and CMD signals from external CLK to the internal used clock signal.
The card is controlled by the three line MultiMediaCard interface containing the signals: CMD, CLK,
DAT (refer to Chapter “Interfaces”). For the identification of the MultiMediaCard in a stack of
MultiMediaCards, a card identification register (CID) and a relative card address register (RCA) are
foreseen. An additional register contains different types of operation parameters. This register is called
card specific data register (CSD). The communication using the MultiMediaCard lines to access either the
memory field or the registers is defined by the MultiMediaCard standard (refer to Chapter
“Communication”). The card has its own power on detection unit. No additional master reset signal is
required to setup the card after power on. It is protected against short circuit during insertion and removal
while the MultiMediaCard system is powered up (refer to Chapter “Power Supply”). No external
programming voltage supply is required. The programming voltage is generated on card.
These Renesas MultiMediaCards support a second interface operation mode the SPI interface mode. The
SPI mode is activated if the CS signal is asserted (negative) during the reception of the reset command
(CMD0) (refer to Chapter “SPI Communication”).
Rev.0.02, Sep.15.2004, page 3 of 89
Generator
V
PP
Flash control
CS CMD/DI
1
Internal clock
CSD[127:0]
RCA[15:0]
OCR[31:0]
CID[127:0]
2
Memory core
3
V
Core control
Interface driver
CC
4
CLK/SCLK
Interface
5
6
DAT/DO
7