M29W128GH70N6F NUMONYX, M29W128GH70N6F Datasheet - Page 13

• Manufacturer Part Number: M29W128GH70N6F
• Manufacturer: NUMONYX

Specifications of M29W128GH70N6F

• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Address Bus: 24/23Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 16M/8M
• Supply Current: 10mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

2
2.1
2.2
2.3
2.4
2.5
2.6
Signal descriptions
See
connected to this device.
Address inputs (A0-A22)
The address inputs select the cells in the memory array to access during bus read
operations. During bus write operations they control the commands sent to the command
interface of the program/erase controller.
Data inputs/outputs (DQ0-DQ7)
The data I/O outputs the data stored at the selected address during a bus read operation.
During bus write operations they represent the commands sent to the command interface of
the internal state machine.
Data inputs/outputs (DQ8-DQ14)
The data I/O outputs the data stored at the selected address during a bus read operation
when BYTE is High, V
impedance. During bus write operations the command register does not use these bits.
When reading the status register these bits should be ignored.
Data inputs/outputs or address inputs (DQ15A 1)
When the device is in x 16 bus mode, this pin behaves as a data input/output pin (as DQ8-
DQ14). When the device operates in x 8 bus mode, this pin behaves as the least significant
bit of the address. Throughout the text consider references to the data input/output to
include this pin when the device operates in x 16 bus mode and references to the address
inputs to include this pin when the device operates in x 8 bus mode except when stated
explicitly otherwise.
Chip enable (E)
The chip enable pin, E, activates the memory, allowing bus read and bus write operations to
be performed. When chip enable is High, V
Output enable (G)
The output enable pin, G, controls the bus read operation of the memory.
Figure 1: Logic
diagram, and
IH
. When BYTE is Low, V
Table 2: Signal
IH
, all other pins are ignored.
IL
, these pins are not used and are high
names, for a brief overview of the signals
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