M25PE80-VMN6P NUMONYX, M25PE80-VMN6P Datasheet - Page 42

• Manufacturer Part Number: M25PE80-VMN6P
• Description: Flash Mem Serial-SPI 3.3V 8M-Bit 1M x 8 8ns 8-Pin SOIC N Tray
• Manufacturer: NUMONYX

Specifications of M25PE80-VMN6P

• Package: 8SOIC N
• Cell Type: NOR
• Density: 8 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 256Byte x 4096
• Timing Type: Synchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Serial-SPI
• Lead Free Status / RoHS Status: Compliant

Instructions
6.14
42/66
Sector erase (SE)
The sector erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the write enable (WREN) instruction has been decoded, the device sets the write
enable latch (WEL).
The sector erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on serial data input (D). Any address inside the
sector (see
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the sector erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed sector erase cycle (whose duration is t
initiated. While the sector erase cycle is in progress, the status register may be read to
check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during
the self-timed sector erase cycle, and is 0 when it is completed. At some unspecified time
before the cycle is complete, the write enable latch (WEL) bit is reset.
A sector erase (SE) instruction applied to a sector that contains a page that is hardware or
software protected is not executed.
Any sector erase (SE) instruction, while an erase, program or write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
If Reset (Reset) is driven Low while a sector erase (SE) cycle is in progress, the sector
erase cycle is interrupted and data may not be erased (see
Reset Low
t
For the value of t
AC
Figure 20. Sector erase (SE) instruction sequence
1. Address bits A23 to A20 are don’t care.
RHSL
parameters.
is then required before the device can be re-selected by driving Chip Select (S) Low.
S
C
D
pulse). On Reset going Low, the device enters the reset mode and a time of
Table
RHSL
5) is a valid address for the sector erase (SE) instruction. Chip Select (S)
see
0
Table 26: Timings after a Reset Low pulse
1
2
Instruction
3
4
Figure
5
6
7
20.
MSB
23 22
8
9
24-bit address
Table 15: Device status after a
2
29 30 31
1
0
in
Section 11: DC and
AI03751D
SE
) is
M25PE80