S29JL032H90TAI210 Spansion Inc., S29JL032H90TAI210 Datasheet - Page 15

• Manufacturer Part Number: S29JL032H90TAI210
• Manufacturer: Spansion Inc.

Specifications of S29JL032H90TAI210

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 22/21Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 3/8.5 to 9.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 4M/2M
• Supply Current: 16mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Not Compliant

8.4
8.5
8.6
8.7
August 31, 2009 S29JL032H_00_B8
Simultaneous Read/Write Operations with Zero Latency
Standby Mode
Automatic Sleep Mode
RESET#: Hardware Reset Pin
This device is capable of reading data from one bank of memory while programming or erasing in the other
bank of memory. An erase operation may also be suspended to read from or program to another location
within the same bank (except the sector being erased).
cycles may be initiated for simultaneous operation with zero latency. I
on page 44
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V
(Note that this is a more restricted voltage range than V
V
requires standard access time (t
before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation
is completed.
I
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for t
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. I
Characteristics on page 44
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V
draws CMOS standby current (I
will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a time of t
system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is
completed within a time of t
RESET# pin returns to V
Refer to
diagram.
CC3
CC
± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device
in
DC Characteristics on page 44
AC Characteristics on page 47
represent the current specifications for read-while-program and read-while-erase, respectively.
IH
D a t a
.
READY
represents the automatic sleep mode current specification.
CC4
CE
(not during Embedded Algorithms). The system can read data t
) for read access when the device is in either of these standby modes,
S h e e t
). If RESET# is held at V
represents the standby current specification.
S29JL032H
for RESET# parameters and to
ACC
RP
+ 30 ns. The automatic sleep mode is independent of the
, the device immediately terminates any operation in
IH
Figure 17.8 on page 52
.) If CE# and RESET# are held at V
IL
READY
but not within V
(during Embedded Algorithms). The
CC6
Figure 17.2 on page 48
and I
SS
CC7
shows how read and write
±0.3 V, the standby current
in
SS
DC Characteristics
±0.3 V, the device
CC5
IH
, but not within
in
for the timing
CC
RH
DC
± 0.3 V.
after the
15