W9751G6JB-3 Winbond, W9751G6JB-3 Datasheet - Page 51

• Manufacturer Part Number: W9751G6JB-3
• Manufacturer: Winbond
• Type: DDR2 SDRAMr

Specifications of W9751G6JB-3

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 14b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: WBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 150mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Clock period jitter
Clock period jitter during DLL locking period
Cycle to cycle clock period
Cycle to cycle clock period jitter during DLL
locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across n cycles,
n = 6 ... 10, inclusive
Cumulative error across n cycles,
n = 11 ... 50, inclusive
Duty cycle jitter
30. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec
Input clock-Jitter specifications parameters for DDR2-667, DDR2-800 and DDR2-1066
Definitions:
- tCK(avg)
- tCH(avg) and tCL(avg)
parameters'. The jitter specified is a random jitter meeting a Gaussian distribution.
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window.
tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.
PARAMETER
tCH(avg) =
tCL(avg) =
tCK(avg) =
tERR(10-50per)
tERR(6-10per)
tJIT(per,lck)
where
where
where
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tJIT(cc,lck)
SYMBOL
tJIT(duty)
tJIT(per)
tJIT(cc)
⎡
⎢
⎣
⎡
⎢
⎣
∑
∑
j
j
N
N
=
=
1
1
tCH
tCL
- 51 -
⎡
⎢
⎣
∑
j
j
j
N
⎤
⎥
⎦
=
⎤
⎥
⎦
N = 200
N = 200
N = 200
1
MIN.
/ (N × tCK(avg))
-125
-100
-250
-200
-175
-225
-250
-250
-350
-450
-125
tCK
/ (N × tCK(avg))
DDR2-667
j
⎤
⎥
⎦
MAX.
125
100
250
200
175
225
250
250
350
450
125
/ N
Publication Release Date: Jun. 18, 2010
MIN.
-100
-200
-160
-150
-175
-200
-200
-300
-450
-100
-80
DDR2-800
MAX.
100
200
160
150
175
200
200
300
450
100
80
W9751G6JB
MIN.
-180
-160
-132
-157
-175
-188
-250
-425
DDR2-1066
-90
-80
-75
Revision A03
MAX.
180
160
132
157
175
188
250
425
90
80
75
UNIT
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS