W9751G6JB-3 Winbond, W9751G6JB-3 Datasheet - Page 3

• Manufacturer Part Number: W9751G6JB-3
• Manufacturer: Winbond
• Type: DDR2 SDRAMr

Specifications of W9751G6JB-3

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 14b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: WBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 150mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

11.
12.
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
10.18
10.19
10.20
10.21
10.22
10.23
10.24
10.25
(AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks).......................................................................................80
10.26
(AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks).......................................................................................81
10.27
10.28
10.29
10.30
10.31
10.32
Package Outline WBGA-84 (8x12.5 mm
Timing of the CLK Signals...................................................................................................................67
ODT Timing for Active/Standby Mode.................................................................................................68
ODT Timing for Power Down Mode ....................................................................................................68
ODT Timing mode switch at entering power down mode ....................................................................69
ODT Timing mode switch at exiting power down mode ......................................................................70
Data output (read) timing ....................................................................................................................71
Burst read operation: RL=5 (AL=2, CL=3, BL=4) ................................................................................71
Data input (write) timing ......................................................................................................................72
PACKAGE SPECIFICATION ..............................................................................................................85
REVISION HISTORY ..........................................................................................................................86
Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4)...........................................................72
Seamless burst read operation: RL = 5 ( AL = 2, and CL = 3, BL = 4) ......................................73
Seamless burst write operation: RL = 5 ( WL = 4, BL = 4).........................................................73
Burst read interrupt timing: RL =3 (CL=3, AL=0, BL=8) .............................................................74
Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL=8) ..................................................74
Write operation with Data Mask: WL=3, AL=0, BL=4) ...............................................................75
Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=4, tRTP ≤ 2clks) ............76
Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) ............76
Burst read operation followed by precharge: RL=5 (AL=2, CL=3, BL=4, tRTP ≤ 2clks) ............77
Burst read operation followed by precharge: RL=6 (AL=2, CL=4, BL=4, tRTP ≤ 2clks) ............77
Burst read operation followed by precharge: RL=4 (AL=0, CL=4, BL=8, tRTP > 2clks) ............78
Burst write operation followed by precharge: WL = (RL-1) = 3 ..................................................78
Burst write operation followed by precharge: WL = (RL-1) = 4 ..................................................79
Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) ...............79
Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=4, tRTP > 2clks) ...............80
Burst read with Auto-precharge followed by an activation to the same bank (tRC Limit): RL=5
Burst read with Auto-precharge followed by an activation to the same bank (tRP Limit): RL=5
Burst write with Auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3.................................81
Burst write with Auto-precharge (WR + tRP Limit): WL=4, WR=2, BL=4, tRP=3 .......................82
Self Refresh Timing ...................................................................................................................82
Active Power Down Mode Entry and Exit Timing.......................................................................83
Precharged Power Down Mode Entry and Exit Timing ..............................................................83
Clock frequency change in precharge Power Down mode ........................................................84
2
).......................................................................................................85
- 3 -
Publication Release Date: Jun. 18, 2010
W9751G6JB
Revision A03