K4H511638C-UCB3 Samsung Semiconductor, K4H511638C-UCB3 Datasheet - Page 4

• Manufacturer Part Number: K4H511638C-UCB3
• Manufacturer: Samsung Semiconductor
• Type: DDR SDRAMr

Specifications of K4H511638C-UCB3

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 185mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

1.0 Key Features
2.0 Ordering Information
3.0 Operating Frequencies
DDR SDRAM 512Mb C-die (x4, x8, x16)
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II
•
RoHS compliant
-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
Speed @CL2.5
CL-tRCD-tRP
Speed @CL2
Speed @CL3
K4H510838C-UC/LCC
K4H511638C-UC/LCC
K4H510438C-UC/LB3
K4H510438C-UC/LA2
K4H510438C-UC/LB0
K4H510838C-UC/LB3
K4H510838C-UC/LA2
K4H510838C-UC/LB0
K4H511638C-UC/LB3
K4H511638C-UC/LA2
K4H511638C-UC/LB0
Part No.
Pb-Free
package
CC(DDR400@CL=3)
166MHz
200MHz
3-3-3
-
128M x 4
32M x 16
64M x 8
Org.
B3(DDR333@CL=2.5)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
133MHz
166MHz
2.5-3-3
Max Freq.
-
A2(DDR266@CL=2.0)
133MHz
133MHz
2-3-3
Interface
-
SSTL2
SSTL2
SSTL2
Rev. 1.2 January 2007
B0(DDR266@CL=2.5)
DDR SDRAM
66pin TSOP II
66pin TSOP II
66pin TSOP II
100MHz
133MHz
2.5-3-3
Package
-