MT49H32M9BM-25 Micron Technology Inc, MT49H32M9BM-25 Datasheet
MT49H32M9BM-25
Specifications of MT49H32M9BM-25
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MT49H32M9BM-25 Summary of contents
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... 1.5V or 1.8V V EXT DD • On-die termination (ODT PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D1.fm - Rev N 5/08 EN Products and specifications discussed herein are subject to change by Micron without notice. 288Mb: x9, x18, x36 2.5V V ® II Figure 1: Options • Clock cycle timing – 2.5ns (400 MHz) – ...
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... Figure 2: 288Mb RLDRAM II CIO Part Numbers Configuration 32 Meg Meg Meg x 36 Notes: 1. The FBGA package is being phased out. BGA Part Marking Decoder Due to space limitations, BGA-packaged components have an abbreviated part marking that is different from the part number. Micron’s BGA Part Marking Decoder is available on Micron’ ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG .66 Disabling the JTAG Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Test Access Port (TAP .66 TAP Controller .67 Performing a TAP RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 TAP Registers .69 TAP Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_CIOTOC.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2. 1. HSTL, CIO, RLDRAM II EXT DD Table of Contents Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... List of Figures Figure 1: 144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Figure 2: 576Mb RLDRAM II CIO Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Figure 3: Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 7: 144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 8: Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Figure 9: Nominal tAS/tCS/tDS and tAH/tCH/tDH Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Figure 10: Example Temperature Test Point Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Figure 12: Read Burst Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Figure 13: On-Die Termination-Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Figure 14: WRITE Command ...
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... Identification Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Table 27: Scan Register Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Table 28: Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Table 29: Boundary Scan (Exit) Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_CIOLOT.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2. 1. HSTL, CIO, RLDRAM II EXT DD Lisf of Tables Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Read and write accesses to the RLDRAM are burst-oriented. The burst length (BL) is programmable from setting the mode register. The device is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output drivers ...
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... State Diagram Figure 3: Simplified State Diagram WRITE PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2.5V V Initialization sequence DSEL/NOP MRS Automatic sequence Command sequence HSTL, CIO, RLDRAM II EXT DD State Diagram READ AREF Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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Functional Block Diagrams Figure 4: 32 Meg x 9 Functional Block Diagram ZQ ODT control CK CK# Control CS# logic REF# WE# Refresh 13 counter Mode register Row- address MUX 18 13 A0–A20 1 Address BA0–BA2 24 register 3 8 ...
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Figure 5: 16 Meg x 18 Functional Block Diagram ZQ ODT control CK CK# Control CS# logic REF# WE# Refresh 13 counter Mode register Row- address MUX 18 13 A0–A19 1 Address 23 BA0–BA2 register Notes: ...
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Figure 6: 8 Meg x 36 Functional Block Diagram ZQ ODT control CK CK# Control CS# logic REF# WE# Refresh 13 counter Mode register Row- address MUX 18 13 A0–A18 1 Address 22 BA0–BA2 register Notes: ...
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... This may optionally be connected to GND not use. This signal is internally connected and has parasitic characteristics of a I/O. This may optionally be connected to GND. Note that if ODT is enabled, these pins will be con- nected to V PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2. ...
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... This may optionally be connected to GND not use. This signal is internally connected and has parasitic characteristics of a I/O. This may optionally be connected to GND. Note that if ODT is enabled, these pins will be con- nected to V PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2. ...
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... EXT Notes: 1. Reserved for future use. This may optionally be connected to GND. 2. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may optionally be connected to GND. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2. ...
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... Output data clocks: QKx and QKx# are opposite polarity, output data clocks. They are free- running, and during READs, are edge-aligned with data output from the RLDRAM. QKx# is ideally 180 degrees out of phase with QKx. For the x36 device, QK0 and QK0# are aligned with DQ0– ...
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... Symbol Type DNU – Do not use: These balls may be connected to ground. Note that if ODT is enabled, these pins will be connected – No function: These balls can be connected to ground. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2.5V V Description . 1. HSTL, CIO, RLDRAM II EXT DD Ball Assignments and Descriptions Micron Technology, Inc ...
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... SMD BALL PAD. 17.00 15.40 8.50 4.40 11.00 ±0.10 Notes: 1. All dimensions are in millimeters. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2.5V V 10º TYP 0.08 MAX 0.80 TYP BALL A1 BALL A1 ID 1.00 TYP 18.50 ±0.10 9.25 ±0.05 5.50 ± ...
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... NSMD BALL PAD. BALL A12 17.00 8.50 4.40 Notes: 1. All dimensions are in millimeters. 2. The FBGA package is being phased out. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2.5V V 0.75 ±0.05 0.155 ±0.013 2.20 ±0.025 CTR 8.80 0.80 TYP BALL A1 BALL A1 ID 9.25 ± ...
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... Measurement is example taken during continuous READ Operating burst Cyclic bank access; Half of address bits read current change every 4 clock cycles; Measurement is example taken during continuous READ PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2. Condition RC ...
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... V/ns in the range between PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2.5V V specifications are tested after the device is properly initialized. +0°C ≤ T ≤ +1.9V, +2.38V ≤ V ≤ +2.63V, +1.4V ≤ V ...
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... Typically the value of V expected to track variations Peak-to-peak AC noise REF DC level of the same. Peak-to-peak noise (non-common mode percent of the DC value. Thus, from V and an additional ±2 percent V nearest V PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2. Conditions Symbol – V EXT – ...
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... V REF from each data input signal to the nearest 125–185Ω at 95° and I are defined as absolute values and are measured flows into the device. OL and V , refer to the RLDRAM II HSPICE or IBIS driver models Symbol (GND and ...
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... IN DC CK# V Q Q MIN IN DC Notes and CK# must cross within this region and CK# must meet at least V 3. Minimum peak-to-peak swing violation to tristate CK and CK# after the part is initialized. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2.5V V Symbol (GND). SS ...
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... CK and CK# cross point). Note: The above descriptions also pertain to data setup and hold derating when CK/CK# are replaced with DK/DK#. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2. specifications when the slew rate of any of these input signals is less than t ...
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... PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2. AS MIN to CK/CK# AH/ Crossing Crossing to V CK, CK# Differential Slew Rate: 2.0 V/ns –100 –100 –100 –100 –100 – ...
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... PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2. MIN to DH CK/CK CK/CK# Crossing Crossing to V DK, DK# Differential Slew Rate: 2.0 V/ns –100 –100 –100 –100 –100 –100 – ...
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... Description Address/control input capacitance Input/output capacitance (DQ, DM, and QK/QK#) Clock capacitance (CK/CK#, and DK/DK#) JTAG pins Notes: 1. Capacitance is not tested on ZQ pin. 2. JTAG pins are tested at 50 MHz. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2. and AH/ CH/ DH Slew Rate ...
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... QKQ0, t QKQ1 t QK edge to any output data edge t QK edge to QVLD QKVLD t DVW Data valid window Refresh t Average periodic refresh interval PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2.5V V -25 Min Max Min t CK 2.5 5 –150 150 –200 PER ...
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... QKQ takes into account the skew between any QKx and any improve efficiency, eight AREF commands (one for each bank) can be posted to the RLDRAM on consecutive cycles at periodic intervals of 3.90µs. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2. the command, address, and data signals ...
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... Table 14. For designs that are expected to last several years and require the flexi- bility to use several DRAM die shrinks, consider using final target theta values (rather than existing values) to account for increased thermal impedances from the die size reduction. The RLDRAM device’ ...
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... Notes: Thermal impedance data is based on a number of samples from multiple lots and should be viewed as a typical number. Figure 11: Example Temperature Test Point Location Test point PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO_D2.fm - Rev N 5/08 EN 288Mb: x9, x18, x36 2.5V V θ JA (°C/W) Airflow = 1m/s 41.2 29.1 28 ...
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... Description of Commands Command DSEL/NOP The NOP command is used to perform a no operation to the RLDRAM, which essentially deselects the chip. Use the NOP command to prevent unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Output values depend on command history. ...
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... During an MRS command, the address inputs A0–A17 are sampled and stored in the mode register. After issuing a valid MRS command, command can be issued to the RLDRAM. This statement does not apply to the consecu- tive MRS commands needed for internal logic reset during the initialization routine. The MRS command can only be issued when all banks are idle and no bursts are in progress ...
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... A10–A17 must be set to zero; A18–An = “Don’t Care.” not used in MRS not available. 4. DLL RESET turns the DLL off. 5. Available in 576Mb part only. 6. ±30 percent temperature variation. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2.5V V A17 A10 17– ...
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... Burst Length (BL) Burst length is defined by M3 and M4 of the mode register. Read and write accesses to the RLDRAM are burst-oriented, with the burst length being programmable Figure 12 on page 34 illustrates the different burst lengths with respect to a READ command. Changes in the burst length affect the width of the address bus (see Table 19 on page 34 for details) ...
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... DRAM. In multiplexed address mode, the address can be provided to the RLDRAM in two parts that are latched into the memory with two consecutive rising clock edges. This provides the advantage of only ...
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... The data bus efficiency in continuous burst mode is only affected when using the setting since the device requires two clocks to read and write the data. The bank addresses are delivered to the RLDRAM at the same time as the WRITE and READ command and the first address part, Ax. Table 21 on page 60 and Table 22 on page 61 show the addresses needed for both the first and second rising clock edges (Ax and Ay, respectively) ...
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... READ command is issued. Similarly, ODT is designed to switch on at the DQs after the RLDRAM has issued the last piece of data. The DM pin will always be terminated. See section entitled “Operations” on page 40 for relevant timing diagrams. Table 20: On-Die Termination DC Parameters Description ...
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... WRITE command. During WRITE commands, data will be registered at both edges of DK according to the programmed burst length (BL). The RLDRAM operates with a WRITE latency (WL) that is one cycle longer than the programmed READ latency (RL + 1), with the first valid data registered at the first rising DK edge WL cycles after the WRITE command ...
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... READ Command CK# CS# WE# REF# ADDRESS BANK ADDRESS PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. QKQ0 is referenced to DQ0–DQ17 for the x36 configuration and DQ0–DQ8 t QKQ1 is the skew between QK1 and the last valid data edge t t QKQ [MAX QKQ [MIN]|). See Figures 28– ...
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... RLDRAM requires 64K cycles at an average periodic interval of 0.49µs MAX (actual periodic refresh interval is 32ms/8K rows/8 banks = 0.488µs). To improve effi- ciency, eight AREF commands (one for each bank) can be posted to the RLDRAM at peri- odic intervals of 3.9µs (32ms/8K rows = 3.90µs). Figure 31 on page 54 illustrates an example of a refresh sequence ...
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... Apply NOP conditions to command pins. Ensuring CK/CK# meet V t MRSC does not need to be met between these consecutive Q before the same level CK/CK# can not be met prior to being applied to the RLDRAM, placing 1. HSTL, CIO, RLDRAM II EXT and start clock as soon as the supply volt- ...
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... CK and CK# must be separated at all times to prevent bogus commands from being issued. 5. The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP com- mands) does not matter required for any operation, AUTO REFRESH command and a subsequent VALID command to the same bank. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. ...
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... The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP com- mands) does not matter required for any operation, AUTO REFRESH command and a subsequent VALID command to the same bank. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. and V ...
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... CKDK (MIN DK CKDK (MAX DK Notes data-in for bank a and address n; subsequent elements of burst are applied follow- ing DI an PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. NOP NOP t CKDK t CKDK HSTL, CIO, RLDRAM II EXT T5n T6 T6n NOP NOP NOP ...
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... Three subsequent elements of the burst are applied following DI for each bank Each WRITE command may be to any bank; if the second WRITE is to the same bank must be met. 5. Nominal conditions are assumed for specifications not defined. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. WRITE NOP WRITE ...
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... Notes data-in for bank a and address data-out from bank b and address n. 3. Two subsequent elements of each burst follow DI an and DO bn Nominal conditions are assumed for specifications not defined. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. READ NOP Bank b, ...
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... Only one NOP separating the WRITE and READ would have led to contention on the data bus because of the input and output data timing conditions being used. 6. Nominal conditions are assumed for specifications not defined. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. ...
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... Bank a, ADDRESS Add n DK Notes data-in for bank a and address n. 2. Subsequent elements of burst are provided on following clock edges Nominal conditions are assumed for specifications not defined. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. NOP NOP NOP 1. HSTL, CIO, RLDRAM II ...
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... DQ t CKQK (MAX) QK# QK QVLD DQ Notes data-out from bank a and address an. 2. Three subsequent elements of the burst are applied following DO an Nominal conditions are assumed for specifications not defined. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. NOP NOP QKH ...
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... Bank address can be to any bank, but the subsequent READ can only be to the same bank has been met. 6. Data from the READ commands to banks c and d will appear on subsequent clock cycles that are not shown. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. READ ...
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... Notes data-out from bank a and address data-in for bank b and address n. 3. Three subsequent elements of each burst follow DI bn and each DO an Nominal conditions are assumed for specifications not defined. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. WRITE NOP ...
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... All DQs and QKs collectively t Notes: 1. QHP is defined as the lesser QKQ0 is referenced to DQ0–DQ8. 3. Minimum data valid window ( t QHP - ( PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. QHP 1 t QHP 1 t QKQ0 (MAX QKQ0 (MAX QKQ0 (MIN QKQ0 (MIN DVW 3 t DVW 3 t QKH or ...
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... QHP - ( t 4. QKQ1 is referenced to DQ9–DQ17 QKQ takes into account the skew between any QKx and any DQ. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. QHP 1 t QHP 1 t QKQ0 (MAX QKQ0 (MAX QKQ0 (MAX QKQ0 (MIN QKQ0 (MIN DVW 3 ...
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... QHP - ( t 4. QKQ1 is referenced to DQ18–DQ35 QKQ takes into account the skew between any QKx and any DQ. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. QHP 1 t QHP 1 t QKQ0 (MAX QKQ0 (MAX QKQ0 (MIN QKQ0 (MIN DVW 3 t DVW 3 ...
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... AUTO REFRESH Cycle COMMAND ADDRESS BANK DK, DK# Notes: 1. AREFx = AUTO REFRESH command to bank x. 2. ACx = any command to bank x; ACy = any command to bank y. 3. BAx = bank address to bank x; BAy = bank address to bank y. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. CK ...
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... QK# QK QVLD DQ DQ ODT Notes data out from bank a and address followed by the remaining bits of the burst. 3. Nominal conditions are assumed for specifications not defined. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. NOP NOP NOP DQ ODT on DQ ODT on DQ ODT ...
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... Notes data-out from bank a and address data-in for bank b and address One subsequent element of each burst appears after each DO an and DI bn. 4. Nominal conditions are assumed for specifications not defined. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. READ NOP ...
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... Command Description in Multiplexed Address Mode READ CK# CK CS# WE# REF# ADDRESS Ax Ay BANK BA ADDRESS Notes: 1. The minimum setup and hold times of the two address parts are defined PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2.5V V WRITE 1. HSTL, CIO, RLDRAM II EXT DD MRS Micron Technology, Inc ...
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... Address A5 must be set HIGH. This and the following step set the desired mode register once the RLDRAM is in multiplexed address mode. 5. Any command or address. 6. The above sequence must be followed in order to power up the RLDRAM in the multiplexed address mode. 7. DLL must be reset and CK# must separated at all times to prevent bogus commands from being issued. ...
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... Ay8 not used in MRS. 6. Available only in 576Mb device. 7. BA0–BA2 are “Don’t Care.” 8. Addresses A0, A3, A4, A5, A8, and A9 must be set as shown in order to activate the mode register in the multiplexed address mode. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2.5V V A18 . . . A10 A9 ...
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... Address Mapping in Multiplexed Address Mode Table 21: 288Mb Address Mapping in Multiplexed Address Mode Data Burst Width Length Ball A0 x36 x18 A20 Notes “Don’t Care.” PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. 1. HSTL, CIO, RLDRAM II EXT DD Address A9 A10 ...
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... Configuration Tables in Multiplexed Address Mode In multiplexed address mode, the read and write latencies are increased by one clock cycle. However, the RLDRAM cycle time remains the same as when in non-multiplexed address mode. Table 22: Cycle Time and READ/WRITE Latency Configuration Table in Multiplexed Mode Parameter ...
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... data-in for bank data-in for bank b. 3. Three subsequent elements of the burst are applied following DI for each bank. 4. Each WRITE command may be to any bank; if the second WRITE is to the same bank, must be met. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. ...
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... One subsequent element of each burst follows DI a and Nominal conditions are assumed for specifications not defined. 6. Bank address can be to any bank, but the subsequent READ can only be to the same bank has been met. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. READ NOP Ax ...
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... Bank address can be to any bank, but the subsequent READ can only be to the same bank has been met. 7. Data from the READ commands to banks b through bank d will appear on subsequent clock cycles that are not shown. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. NOP ...
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... Three subsequent elements of the burst which appear following DI bn are not all shown. 7. Bank address can be to any bank, but the WRITE command can only be to the same bank has been met. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2. ...
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... M8 needs to be set to 0 until the JTAG testing of the pin is complete. Note that upon power up, the default state of MRS bit M8 is low. If the RLDRAM boundary scan register used upon power up and prior to the initialization of the RLDRAM device imperative that the CK and CK# pins meet V (DC) or CS# be held HIGH from power up until testing ...
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... When shifting is to reconvene, the controller enters the exit2-DR state and then can re-enter the shift-DR state. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2.5V V IEEE 1149.1 Serial Boundary Scan (JTAG ...
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... Figure 43: TAP Controller State Diagram Test-logic 1 0 Figure 44: TAP Controller Block Diagram TDI TCK TMS Notes 112 for all configurations. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2.5V V IEEE 1149.1 Serial Boundary Scan (JTAG) reset Select Run-test/ Idle DR-scan 0 1 ...
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... Table 29 on page 74 shows the order in which the bits are connected. Each bit corre- sponds to one of the balls on the RLDRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state when the IDCODE command is loaded in the instruction register ...
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... The user must be aware that the TAP controller clock can only operate at a frequency MHz, while the RLDRAM clock operates significantly faster. Because there is a large difference between the clock frequencies possible that during the capture-DR state, an input or output will undergo a transition ...
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... STATE TDO T10 T11 TCK TMS TDI TAP Select-DR- CONTROLLER Exit 2-IR Update-IR STATE TDO PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2.5V V IEEE 1149.1 Serial Boundary Scan (JTAG Select-DR- Select-IR- Capture-IR SCAN SCAN T12 T13 T14 T15 Capture-DR ...
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... TCK HIGH to TDI invalid Setup times TMS setup Capture setup Hold times TMS hold Capture hold t Notes and ary scan register. PDF: 09005aef80a41b59/Source: 09005aef809f284b 288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN 288Mb: x9, x18, x36 2.5V V IEEE 1149.1 Serial Boundary Scan (JTAG Test clock (TCK THTL TLTH t MVTH t THMX ...
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... DD All Devices abcd ab = die revision for x9, 01 for x18, 10 for x36 00jkidef10100111 def = 000 for 288Mb, 001 for 576Mb for common I/O, 1 for separate I for RLDRAM II, 00 for RLDRAM 00000101100 Allows unique identification of RLDRAM vendor 1 Indicates the presence register HSTL, CIO, RLDRAM II ...
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... This operation does not affect RLDRAM operations Loads the ID register with the vendor ID code and places the register between TDI and TDO; This operation does not affect RLDRAM operations Captures I/O ring contents; Places the boundary scan register between TDI and TDO Selects the bypass register to be connected between TDI and TDO ...
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... Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. RLDRAM is a trademark of Qimonda AG in various countries, and is used by Micron Technology, Inc. under license from Qimonda. All other trademarks are the property of their respective owners ...