K4D263238KVC50 Samsung Semiconductor, K4D263238KVC50 Datasheet - Page 3

• Manufacturer Part Number: K4D263238KVC50
• Manufacturer: Samsung Semiconductor
• Type: FPMr

Specifications of K4D263238KVC50

• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 700ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.625V
• Operating Supply Voltage (min): 2.375V
• Supply Current: 60mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
FEATURES
ORDERING INFORMATION
GENERAL DESCRIPTION
K4D263238K
• 2.5V ± 5% power supply for device operation
• 2.5V ± 5% power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except data & DM are sampled at the positive
• Differential clock input
• Write Interrupted by Read function
FOR 1M x 32Bit x 4 Bank DDR SDRAM
The K4D263238K is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by
32 bits, fabricated with SAMSUNG
extremely high performance up to
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
going edge of the system clock
K4D263238K-GC is the Leaded package part number.
-. Read latency 3 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
K4D263238K-VC40
K4D263238K-VC50
Part NO.
2.0GB/s/chip.
′
s high performance CMOS technology. Synchronous features with Data Strobe allow
Max Freq.
250MHz
200MHz
I/O transactions are possible on both edges of the clock cycle. Range of
- 3/19 -
Max Data Rate
500Mbps/pin
400Mbps/pin
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• 144pin FBGA package
• Maximum clock frequency up to 250MHz
• Maximum data rate up to 500Mbps/pin
Interface
SSTL_2
128M GDDR SDRAM
Rev. 1.2 October 2007
144FBGA
Package