K4D263238KVC50 Samsung Semiconductor, K4D263238KVC50 Datasheet - Page 14

• Manufacturer Part Number: K4D263238KVC50
• Manufacturer: Samsung Semiconductor
• Type: FPMr

Specifications of K4D263238KVC50

• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 700ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.625V
• Operating Supply Voltage (min): 2.375V
• Supply Current: 60mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

tQH Timing (CL3, BL2)
K4D263238K
Note 1 :
- A new AC timing term, tQH which stands for data output hold time from DQS is defined to account for clock duty cycle
- tQHmin = tHP-X where
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
COMMAND
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
variation and replaces tDV
strobe and all data associated with that data strobe are coincidentally valid.
output valid window even then the clock duty cycle applied to the device is better than 45/55%
CK, CK
DQS
DQ
CS
READA
0
1
1
2
- 14/19 -
tDQSQ(max)
3
Da0
tQH
tHP
tDQSQ(max)
Da1
4
128M GDDR SDRAM
Rev. 1.2 October 2007
5