K4S281632K-UC75T00 Samsung Semiconductor, K4S281632K-UC75T00 Datasheet - Page 15

• Manufacturer Part Number: K4S281632K-UC75T00
• Manufacturer: Samsung Semiconductor
• Type: SDRAMr

Specifications of K4S281632K-UC75T00

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 140mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

K4S280832K
K4S281632K
18.0 Simplified Truth Table
Register
Refresh
Bank active & row addr.
Read &
column address
Write &
column address
Burst stop
Precharge
Clock suspend or
active power down
Precharge power down mode
DQM
No operation command
Notes :
1. OP Code : Operand code
2. MRS can be issued only at all banks precharge state.
3. Auto refresh functions are as same as CBR refresh of DRAM.
4. BA0 ~ BA1 : Bank select addresses.
5. During burst read or write with auto precharge, new read/write command can not be issued.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
A new command can be issued after 2 CLK cycles of MRS.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Command
Mode register set
Auto refresh
Self
refresh
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
Bank selection
All banks
Entry
Entry
Entry
Exit
Exit
Exit
CKEn-1
H
H
H
H
H
H
H
H
H
H
H
L
L
L
CKEn
X
H
H
H
H
L
X
X
X
X
X
L
L
X
15 of 15
CS
H
H
H
H
H
X
L
L
L
L
L
L
L
L
L
L
L
L
RAS
X
H
X
H
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
CAS
H
X
H
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
WE
H
H
H
H
H
H
L
X
X
V
X
X
X
V
X
L
L
L
DQM
X
X
X
X
X
X
X
X
X
X
X
X
V
X
Synchronous DRAM
Rev. 1.23 March 2009
BA
V
V
V
V
X
0,1
A
OP code
10
H
H
H
Row address
L
L
L
/AP
X
X
X
X
X
X
X
A
Column
address
Column
address
0
A
~ A
X
11,
9,
Note
1,2
4,5
4,5
3
3
3
3
4
4
6
7