MT48LC8M16A2P-7E:G Micron Technology Inc, MT48LC8M16A2P-7E:G Datasheet - Page 17

• Manufacturer Part Number: MT48LC8M16A2P-7E:G
• Description: IC, SDRAM 128MB, SMD, 48LC8, TSOP54
• Manufacturer: Micron Technology Inc
• Type: SDRAMr
• Series: -r

Specifications of MT48LC8M16A2P-7E:G

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 165mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Access Time: RoHS Compliant
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Operating Temperature Max: 70°C
• Operating Temperature Min: 0°C
• Package / Case: TSOP
• Memory Type: SDRAM
• Memory Configuration: 4 BLK (2M X 16)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Format - Memory: RAM
• Memory Size: 128M (8Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / RoHS Status: Compliant
• Lead Free Status / RoHS Status: Compliant

Burst Type
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
When a READ or WRITE command is issued, a block of columns equal to the BL is effec-
tively selected. All accesses for that burst take place within this block, meaning that the
burst will wrap within the block if a boundary is reached. The block is uniquely selected
by A1–A9, A11 (x4), A1–A9 (x8), or A1–A8 (x16) when BL = 2; by A2–A9, A11 (x4), A2–A9
(x8), or A2–A8 (x16) when BL = 4; and by A3–A9, A11 (x4), A3–A9 (x8), or A3–A8 (x16)
when BL = 8. The remaining (least significant) address bit(s) is (are) used to select the
starting location within the block. Full-page bursts wrap within the page if the boundary
is reached.
Accesses within a given burst may be programmed either to be sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the BL, the burst type, and the
starting column address, as shown in Table 5 on page 19.
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x4, x8, x16 SDRAM
Functional Description
©1999 Micron Technology, Inc. All rights reserved.