S71WS512ND0BFWEP0 Spansion Inc., S71WS512ND0BFWEP0 Datasheet - Page 6

• Manufacturer Part Number: S71WS512ND0BFWEP0
• Manufacturer: Spansion Inc.

Specifications of S71WS512ND0BFWEP0

• Operating Supply Voltage (max): 1.95V
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3.
4
Input/Output Descriptions
Table 3.1
A23-A0
DQ15-DQ0
OE#
WE#
V
NC
RDY
CLK
AVD#
F-RST#
F-WP#
F-ACC
R-CE1#
F1-CE#
F2-CE#
R-CRE
F-VCC
R-VCC
R-UB#
R-LB#
DNU
SS
Symbol
identifies the input and output package connections provided on the device.
Address inputs
Data input/output
Output Enable input. Asynchronous relative to CLK for the Burst mode.
Write Enable input.
Ground
No Connect; not connected internally
Ready output. Indicates the status of the Burst read. The WAIT# pin of the pSRAM is tied to RDY.
Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal
address counter. Should be at V
Address Valid input. Indicates to device that the valid address is present on the address inputs.
Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched.
High = device ignores address inputs
Hardware reset input. Low = device resets and returns to reading array data
Hardware write protect input. At V
at V
Accelerated input. At V
disables all program and erase functions. Should be at V
Chip-enable input for pSRAM.
Chip-enable input for Flash 1. Asynchronous relative to CLK for Burst Mode.
Chip-enable input for Flash 2. Asynchronous relative to CLK for Burst Mode. This applies to the 512Mb MCP only.
Control Register Enable (pSRAM). For CellularRAM only.
Flash 1.8 Volt-only single power supply.
pSRAM Power Supply.
Upper Byte Control (pSRAM).
Lower Byte Control (pSRAM)
Do Not Use
IH
for all other conditions.
HH
Table 3.1 Input/Output Descriptions
, accelerates programming; automatically places device in unlock bypass mode. At V
S71WS-N
IL
IL
or V
D a t a
, disables program and erase functions in the four outermost sectors. Should be
IH
while in asynchronous mode
S h e e t
Description
IH
for all other conditions.
S71WS-N_00_A7 April 4, 2008
IL
,