RD38F2020W0YBQ0 SB93 Micron Technology Inc, RD38F2020W0YBQ0 SB93 Datasheet - Page 33

• Manufacturer Part Number: RD38F2020W0YBQ0 SB93
• Manufacturer: Micron Technology Inc

Specifications of RD38F2020W0YBQ0 SB93

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

128-Mbit W18 Family with Synchronous PSRAM
Warning:
8.2
8.2.1
Warning:
8.2.2
November 2007
Order Number: 311760-10
Except for A19 and A18, all other address and data bits are don’t care. A19 and A18
specify the target register (RCR = 00b, BCR = 10b) The contents of the selected
register are available on the data bus after the specified access time has elapsed. WAIT
output will be driven but should be ignored for asynchronous operations.
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data
phase cycle.
PSRAM Writes
The PSRAM bus interface supports asynchronous single-word and synchronous burst-
mode writes. BCR15 defines whether asynchronous or synchronous mode is enabled.
PSRAM Asynchronous Write
In the Asynchronous (SRAM-type) mode and NOR-Flash mode, PSRAM write commands
are asynchronous. To initiate an asynchronous write operation:
The data to be written will be latched on the rising edge of CE#, WE# or UB#/LB#
whichever occurs first. WAIT output will be driven but should be ignored for
asynchronous-mode operations.
When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen
(16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data
phase cycle.
PSRAM Synchronous Write
In the Full Synchronous mode, PSRAM write operations are synchronous. A BURST INIT
WRITE command is used to initiate a synchronous write operation and latch the burst
start address. To initiate a synchronous write operation:
To continue the synchronous write operation:
The first data word is input after the number of clock cycles defined by the
programmed latency mode and latency count in the BCR. Subsequent data words are
input at successive clock cycles after the first data word. The size of the burst is also
specified in the BCR. WAIT output will be driven and may be monitored. But since
• CLK must be held in a static low state.
• CE# and WE# must be asserted;
• UB# and LB# must be asserted appropriately depending on the data byte(s) that
• CRE must be deasserted;
• ADV# can be toggled to latch the address or held low for the entire read operation;
• CLK must be held in a static state.
• CE#, ADV#, and WE# must be asserted;
• OE# and CRE must be deasserted; and
• Burst start address is latched on the rising edge of the clock;
• CE#, and UB#/LB# must be asserted; and
• ADV# must be deasserted;
are being written. UB# enables DQ[15:8] and LB# enables DQ[7:0].
Datasheet
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