RD38F2020W0YBQ0 SB93 Micron Technology Inc, RD38F2020W0YBQ0 SB93 Datasheet
RD38F2020W0YBQ0 SB93
Specifications of RD38F2020W0YBQ0 SB93
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RD38F2020W0YBQ0 SB93 Summary of contents
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Numonyx™ Wireless Flash Memory (W18 SCSP) 128-Mbit W18 Family with Synchronous PSRAM Product Features Device Architecture — Flash Die Density: 32 128-Mbit — PSRAM Die Density 32-Mbit — x16 Non-Mux or ADMux I/O Interface Option — ...
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR Legal L ines and D isc laim er s OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT ...
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W18 Family with Synchronous PSRAM Contents 1.0 Introduction .............................................................................................................. 6 1.1 Nomenclature ..................................................................................................... 6 1.2 Acronyms........................................................................................................... 7 1.3 Conventions ....................................................................................................... 7 2.0 Functional Overview .................................................................................................. 8 2.1 Product Description ............................................................................................. 8 2.2 Device Combinations ........................................................................................... 9 2.3 Device Operation ...
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PSRAM Power-Up Sequence and Initialization .............................................37 9.2 PSRAM Operating Modes .....................................................................................37 9.3 PSRAM Control Registers ....................................................................................38 9.3.1 PSRAM Bus Control Register .....................................................................38 9.3.2 PSRAM Refresh Control Register ...............................................................42 9.4 PSRAM Access to Control Register ........................................................................45 9.4.1 PSRAM Hardware Control ...
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W18 Family with Synchronous PSRAM Revision History Date Revision February 2006 001 Initial release • Corrected flash and PSRAM specification of CLK from 66 MHz to 54 MHz, and flash burst-mode read timing from ns. ...
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Introduction The 128-Mbit Numonyx™ Wireless Flash memory with synchronous PSRAM stacked device family offers multiple high-performance solutions. The W18 (Non-Mux or AD Mux I/O interface option) highlighted features like asymmetrical block array, configurable burst lengths, security using OTP and ...
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W18 Family with Synchronous PSRAM 1.2 Acronyms APS Automatic Power Savings EFA Extended Flash Array BCR (PSRAM) Bus Control Register Buffered EFP Buffered Enhanced Factory Programming CR (Flash) Configuration Register CSP Chip Scale Package MLC Multi-Level Cell OTP One-Time ...
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Functional Overview 2.1 Product Description The W18 family with synchronous PSRAM stacked product family encompasses multiple W18 flash memory plus synchronous PSRAM die combinations. maximum configuration options for W18 non-multiplex I/O (standard) product and Figure 2 shows the maximum ...
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W18 Family with Synchronous PSRAM Figure 2: W18 ADMux I/O Interface Product Family with Sync PSRAM Block Diagram F1-CE# F1-OE# CLK WAIT ADV# F-WP# F-WE# P-CS# R-OE# P-CRE R-WE# Notes: 1. F2-OE# must be treated as RFU. However, for ...
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Device Operation Overview The following sections describes the bus operations and device state between the flash and synchronous PSRAM. 2.3.1 Flash and Synchronous PSRAM Bus Operations Bus operations for the W18 stacked device involve the control of flash and ...
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W18 Family with Synchronous PSRAM Table 3: PSRAM Bus Operation Operation Power State Modes Mode Read Asynchronous Active Asynchronous Write Active NOR-Flash Asynchronous Set Control Active Register NOR-Flash Fetch Control Asynchronous Active Register Asynchronous No Standby Synchronous Operation /Active ...
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Device Package Information Figure 3: Mechanical Specifications for QUAD+ Ballout Package (8x10x1.2 mm) A1 Index Mark Top View - Ball A2 Dimensions Package Height ...
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W18 Family with Synchronous PSRAM 4.0 Ballout and Signal Descriptions 4.1 Device Signal Ballout Figure 4: QUAD+ Ballout Pin A18 C A5 R-LB A17 ...
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Signal Descriptions Table 4: Signal Descriptions (Sheet Symbol Type Address and Data Signals, Non-Mux ADDRESS: Global device signals. Shared address inputs for all memory die during Read and Write operations. • 128-Mbit: AMAX = A22 • ...
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W18 Family with Synchronous PSRAM Table 4: Signal Descriptions (Sheet Symbol Type RAM OUTPUT ENABLE: PSRAM- and SRAM-specific signal; low-true input. When low, R-OE# enables the output drivers of the selected memory die. When high, R-OE# ...
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Table 4: Signal Descriptions (Sheet Symbol Type I/O POWER SUPPLY: Global device I/O power. VCCQ Power VCCQ supplies the device input/output driver voltage. PSRAM CORE POWER SUPPLY: PSRAM specific. P-VCC Power P-VCC supplies the core power to ...
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W18 Family with Synchronous PSRAM 5.2 Device Operating Conditions Warning: Operation beyond the Operating Conditions is not recommended and extended exposure may affect device reliability. Table 6: Device Operating Conditions Symbol T Device Case Operating Temperature C F-V Flash ...
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Table 7: PSRAM DC Characteristics (Sheet Input Low Voltage IL V Output High Voltage OH V Output Low Voltage OL I Input Leakage Current IL I Output Leakage Current OL I Async Random Read/Write @ T ...
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W18 Family with Synchronous PSRAM 6.3 Device AC Test Conditions Figure 5: Device Transient Equivalent Testing Load Circuit I Notes: 1. Test configuration component value for worst case speed conditions includes ...
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Table 11: PSRAM AC Characteristics—Asynchronous Read Symbol t Read Cycle Time RC t Address Access Time AA t ADV# Access Time AADV t Page Address Cycle Time PC t Page Address Access Time PAA t Address Hold from ADV# High ...
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W18 Family with Synchronous PSRAM Figure 6: Address Skew for Asynchronous Operations Address ADV# (case 1) CE# (case 1) ADV# (case 2) CE# (case 2) Figure 7: PSRAM Asynchronous Single-Word Read tAA A[MAX:0] tAADV ADV# tCO CE# OE# W ...
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Figure 8: Asynchronous Address-controlled Read A[MAX:0] tOH DQ[15:0] Previous Data Note: CE# = OE# = UB# =LB# = CRE = Low; WE# = High Figure 9: PSRAM Asynchronous Page-Mode Read A[MAX:0] tAA A3-A0 ADDRESS tVPH tVPH tAADV ADV# tCO P-CS# ...
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W18 Family with Synchronous PSRAM Figure 10: PSRAM Asynchronous Control Register Read A[19:18] A[M AX:20,17:0] tCRES CE# OE# WE# UB#/LB# DQ[15:0] 7.3 PSRAM Asynchronous Write The figures and tables below shows the PSRAM AC characteristics. ...
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Table 12: PSRAM AC Characteristics—Asynchronous Write (Sheet Symbol t UB#, LB# and CE# Pulse Width High CPH t Write Enable Low to Output High-Z WHZ t End of Write to Output Low Write Data Setup ...
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W18 Family with Synchronous PSRAM Figure 12: PSRAM Asynchronous CE# controlled Write A[MAX:0] ADV# tAS CE# WE# UB#/LB# tBLZ tLZ DQ[15:0] Figure 13: PSRAM Asynchronous UB#/LB# controlled Write A[MAX:0] ADV# tAS CE# WE# UB#/LB# tBLZ tLZ DQ[15:0] November 2007 ...
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Figure 14: PSRAM Asynchronous ADV# controlled Write A[MAX:0] ADV# CE UB#/LB# tBLZ tLZ DQ[15:0] Figure 15: PSRAM Asynchronous Control Register Write A[MAX:0] tCRES CRE ADV# tAS CE# tAS WE# UB#/LB# DQ[15:0] 7.4 PSRAM Synchronous Read and Write The ...
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W18 Family with Synchronous PSRAM Table 13: PSRAM AC Characteristics—Synchronous Read and Write Symbol f CLK Frequency (Variable Latency = 2) Non-Mux and AD Mux CLK2 f CLK Frequency (Fixed Latency = 6) Non Mux and AD Mux CLK6 ...
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Figure 16: Address Skew for Synchronous Operations CLK Address ADV# (Case 1) CE# (Case 1) ADV# (Case 2) CE# (Case 2) Figure 17: PSRAM Synchronous Read followed by Synchronous Write CLK tHD tSP tAVH A[MAX:0] tHD tSP ADV# tCSS CE ...
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W18 Family with Synchronous PSRAM Figure 18: PSRAM Synchronous Write followed by Synchronous Read tHD tS P tAV H A[MA X:0] tHD tS P ADV # tCS tHD tHD ...
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Figure 20: PSRAM Asynchronous Write followed by Synchronous Read : tAS #/ tLZ D Q ...
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W18 Family with Synchronous PSRAM Figure 22: PSRAM Synchronous Control Register Write ...
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Valid data is available on the data bus after the specified access time has elapsed. WAIT output is driven, but should be ignored for asynchronous-mode read operations. Warning: When operating the PSRAM as an ADMux I/O interface by connecting the ...
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W18 Family with Synchronous PSRAM • CLK must be held in a static low state. Except for A19 and A18, all other address and data bits are don’t care. A19 and A18 specify the target register (RCR = 00b, ...
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Latency Mode setting, WAIT may be ignored. UB# or LB# may be deasserted to mask the associated data byte. Warning: When operating the PSRAM as an ADMux I/O interface by ...
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W18 Family with Synchronous PSRAM • In Synchronous mode, ADV# deasserted hold time (tHD) must be observed. Warning: When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen (16) addresses, A[15:0], to the data pins, ...
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Figure 23: PSRAM WAIT Behavior during Burst Write End-of-Row with Wrap Off CLK CE# WAIT DQ[15:0] End of Row Figure 24: PSRAM WAIT Behavior during Burst Read End-of-Row with Wrap Off CLK CE# WAIT DQ[15:0] During variable latency burst write ...
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W18 Family with Synchronous PSRAM 9.0 Device Operations Note: Refer to the Numonyx™ Wireless Flash Memory Datasheet for detailed flash die information. PSRAM device operations are described in the sections that follow. 9.1 Device Power-Up/Down 9.1.1 Flash Power and ...
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PSRAM Control Registers The PSRAM includes two control registers that define the PSRAM device operation. The Bus Control Register (BCR) defines how the PSRAM interacts with the system memory busy, and the Refresh Control Register (RCR) defines low-power refresh ...
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W18 Family with Synchronous PSRAM Table 15: Bus Control Register Description BCR Bit NAME 13:11 Latency Counter 10 WAIT Polarity 9 Reserved 8 WAIT Configuration 7:6 Reserved 5:4 Drive Strength 3 Burst Wrap 2:0 Burst Length 9.3.1.1 PSRAM BCR ...
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Warning: When operating the PSRAM as an ADMux I/O interface by connecting the lower sixteen (16) addresses, A[15:0], to the data pins, ADV# must be de-asserted during any data phase cycle. 9.3.1.2 PSRAM Initial Latency BCR Bit The PSRAM latency ...
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W18 Family with Synchronous PSRAM Figure 26: Example of the Latency of First Valid Data in Synchronous Mode 9.3.1.4 PSRAM WAIT Polarity BCR Bit The WAIT polarity control bit allows the user to define the polarity of the WAIT ...
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Fixed Length Burst with Wrap Off will increment the address until a row boundary crossing is reached. Fixed Length Bursts will continue to wrap around and cycle through their limited address space until terminated or interrupted. The burst length setting ...
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W18 Family with Synchronous PSRAM Table 19: PSRAM Refresh Control Register Map Register Reserved Select DQ[15:0] A[MAX:0 A22 - A20 A19 A18 ] RCR Bit Table 20: PSRAM Refresh Control Register Description RCR Bit ...
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Deep Power Down Entry: To enter deep power down, RCR4 is set low, CE# is then pulled high and is maintained high for the entire time duration that Deep Power Down mode is desired. To insure proper operation, once CE# ...
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W18 Family with Synchronous PSRAM Table 21: PASR Address Pattern for PSRAM Device Mbit ...
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To insure predictable device behavior, the fourth access cycle of the software access should not be terminated or interrupted prematurely and ADV# should not go low more than one time during each access where CE# is low Figure 28: ...
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W18 Family with Synchronous PSRAM Table 22: Cautionary Command Sequences Cautionary Command Sequence #1 Cautionary Command Sequence #2 9.5 PSRAM Self-Refresh Operation Unlike DRAMs, The PSRAM relieves the host system from issuing refresh commands. Self-refresh operations are autonomously scheduled ...
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Figure 30: Example of PSRAM Burst Suspend with Read Burst with Latency Code 2 CLK A[MAX:0] ADV# tCSS CE# OE# WE# UB#/LB# tCWT WAIT DQ[15:0] Note: WAIT is configured as Active Low and asserted during delay. 9.6.2 PSRAM Burst Interrupt ...
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W18 Family with Synchronous PSRAM Figure 31: Example of PSRAM Burst Interrupt ntrol Burst Init 9.6.3 PSRAM Burst Termination A burst access is terminated by bringing CE# high ...
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Figure 32: Terminating or Interrupting Burst Prior to Row Boundary Crossing t-1 10.0 Additional Information : Order Number Document ® 290701 Intel Wireless Flash Memory ...
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W18 Family with Synchronous PSRAM 11.0 Ordering Information To order samples, obtain datasheets or inquire about any stack combination, please contact your local Numonyx representative. Table 23: 38F Type Stacked Components PF 38F 5070 Product Die/ Package Product Line ...
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Table 24: 48F Type Stacked Components PC 48F 4400 Product Die/ Package Product Line Density Designator Designator Configuration PC = Easy BGA, Char 1 = Flash RoHS die # Char 2 = Flash die #2 Easy BGA, Leaded ...
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W18 Family with Synchronous PSRAM Table 26: NOR Flash Family Decoder Code Family C C3 J3v L18 / L30 M M18 P P30 / P33 W W18 / W30 0(zero) - Table 27: Voltage / NOR Flash ...
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Table 28: Parameter / Mux Configuration Decoder Code, Mux Number of Flash Die Identification Non Mux Mux "Full" Mux Only Flash is Muxed and RAM ...