PF38F2030W0YTQ2 Micron Technology Inc, PF38F2030W0YTQ2 Datasheet - Page 6

• Manufacturer Part Number: PF38F2030W0YTQ2
• Manufacturer: Micron Technology Inc

Specifications of PF38F2030W0YTQ2

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

1.0
1.1
Datasheet
6
1.8 Volt Core
1.8 Volt I/O
ADMux I/O
Asserted
Block
Deasserted
Device
Die
High-Z
Low-Z
Non-Array
Reads
Non-Mux I/O
Partition
Program
Write
Introduction
The 128-Mbit Numonyx™ Wireless Flash memory with synchronous PSRAM stacked
device family offers multiple high-performance solutions. The W18 (Non-Mux or AD
Mux I/O interface option) highlighted features like asymmetrical block array,
configurable burst lengths, security using OTP and zero-latency block lock. The W18
delivers up to 66 MHz synchronous burst and page-mode read rates with multi-
partitioning Read-While-Write and Read-While-Erase operations. The synchronous
PSRAM (Non-Mux and AD-Mux I/O interface) is a high-performance volatile memory
operating at speeds up to 66 MHz with configurable burst lengths. The PSRAM lower
sixteen addresses can be routed to the data pins on the PCB board to enable a flexible
flash and PSRAM A/D-Mux I/O interface device design. The W18 stacked device
features 1.8 volt low-voltage operation in an Numonyx™ QUAD+ standard footprint and
signal ballouts.
This document contains information pertaining to the 128-Mbit Title stacked device
family. The W18 is available as a Non-Multiplex or Address-Data Muxltiplex (ADMux) I/
O interface option, while the synchronous PSRAM is available only as a Non-Multiplex I/
O interface. The intent of this document is to provide information where this product
differs from the Intel
Refer to the latest revision of the Intel
Datasheet (order number: Non-Mux I/O doc #290701 and ADMux I/O doc #313272)
for specific flash product details not included in this document.
Nomenclature
VCC (memory subsystem die core) voltage range of 1.7 V – 1.95 V.
VCCQ (memory subsystem I/O) voltage range of 1.7 V – 1.95 V.
Address-Data Multiplex I/O interface, where the lower sixteen (16) addresses are
multiplexed on the data pins (DQ[15:0]) during any address cycle.
Signal with logical voltage level V
Group of cells, bits, bytes, or words within the flash memory array that get erased
with one erase instruction.
Signal with logical voltage level VIH or disabled.
A specific memory type or stacked flash and xRAM memory density configuration
combination within a memory subsystem product family.
Individual flash or xRAM die used in a stacked package memory device.
High Impedance.
Signal is Driven on the bus.
Flash reads which return flash Device Identifier, CFI Query, Protection Register, and
Status Register information.
Traditional parallel flash interface where address are not multiplex onto the data
pins. All address and data pins are unique.
A group of flash blocks that shares common status register read state.
An operation to Write data to the flash array or xRAM.
Bus cycle operation at the inputs of the flash or xRAM die, in which a command or
data are sent to the flash array or xRAM.
®
Wireless Flash Memory (W18) device.
IL
, or enabled.
®
Wireless Flash Memory (W18) Discrete
128-Mbit W18 Family with Synchronous PSRAM
Order Number: 311760-10
November 2007