PF38F2030W0YTQ2 Micron Technology Inc, PF38F2030W0YTQ2 Datasheet - Page 31

• Manufacturer Part Number: PF38F2030W0YTQ2
• Manufacturer: Micron Technology Inc

Specifications of PF38F2030W0YTQ2

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

128-Mbit W18 Family with Synchronous PSRAM
Figure 22: PSRAM Synchronous Control Register Write
8.0
Note:
8.1
8.1.1
November 2007
Order Number: 311760-10
A [ M A X :0 ]
U B # /L B #
D Q [1 5 : 0 ]
Device Bus Interface
Refer to the Numonyx™ Wireless Flash Memory Datasheet for detailed flash die
information.
The PSRAM Bus Interface is described in the sections that follow. The PSRAM bus
interface supports asynchronous and synchronous read and write transfers. By default
the PSRAM device is reset to the asynchronous SRAM-type mode after power-up. To
put the device in a different operation mode the Bus Configuration Register must be
programmed first accordingly.
PSRAM Reads
The PSRAM bus interface supports asynchronous single-word, asynchronous page-
mode, and synchronous burst-mode reads. PSRAM Refresh Control Register bit 7
(RCR7) defines whether page-mode reads are enabled. Page-mode reads are enabled
when RCR7 is set to a one, and disabled when RCR7 is set to zero.
PSRAM Asynchronous Read
To initiate an asynchronous read operation:
A D V #
W A IT
C R E
• CE#, OE#, and UB#/LB# must be asserted.
• WE# and CRE must be deasserted.
• ADV# can be toggled to latch the address or held low for the entire read operation.
• CLK must be held in a static state.
W E #
C L K
C E #
O E #
tC S S
t S P
t S P
t S P
t S P
t S P
tC W T
t H D
t H D
t H D
tH D
tH D
tA V H
tW K
t H D
t H D
t W Z
t C B P H
t C B P H
Datasheet
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